Patents by Inventor Claudia Stanley
Claudia Stanley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7904869Abstract: A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.Type: GrantFiled: December 18, 2007Date of Patent: March 8, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Kathleen C. Yu, Scott D. Hector, Robert L. Maziasz, Claudia A. Stanley, James E. Vasck
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Publication number: 20090158229Abstract: A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.Type: ApplicationFiled: December 18, 2007Publication date: June 18, 2009Inventors: Kathleen C. Yu, Scott D. Hector, Robert L. Maziasz, Claudia A. Stanley, James E. Vasck
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Patent number: 7183798Abstract: Systems and methods are disclosed herein to provide improved memory techniques for logic blocks within a programmable logic device. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a first and a second logic slice adapted to receive a first and a second clock signal. The first and second logic slices may be combined to form wider and deeper memory and single port or synchronous dual port memory.Type: GrantFiled: January 24, 2005Date of Patent: February 27, 2007Assignee: Lattice Semiconductor CorporationInventors: Xiaojie He, Sajitha Wijesuriya, Claudia Stanley, John Schadt
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Publication number: 20050093577Abstract: Multiplexer circuits are disclosed, such as for example for programmable logic devices. As an example of one embodiment, a multiplexer circuit is disclosed having a default state and a state-locking latch.Type: ApplicationFiled: November 4, 2003Publication date: May 5, 2005Inventors: Liem Nguyen, Xiaojie He, Brian Gaide, Kerry Ilgenstein, Sajitha Wijesuriya, Claudia Stanley, Aaron Rogers, Zheng Chen
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Patent number: 6653860Abstract: An improved, high density CPLD includes a plurality of macrocell sections. Each macrocell section can receive a relatively large number of independent input terms and can generate as a base cluster, at least as many as 5 different product term signals (PT's) therefrom. Part or all of the macrocell's local 5 PT's may be used for generating a local sum-of-products (SoP) signal in a local, first-level ORring operation. Additionally SoP's generated in neighboring macrocell sections may be selectively and incrementally cascaded (cross-laced) for supplemental summing into the local SoP signal. SoP signals of neighboring sections may be further selected in a sums sharing array for second level summing. The combination of the first-level cascading (cross-lacing) and second-level sums sharing provides a wide range of programmably selectable granulations including that of having relatively fast generation of a sum of just a few PT's (e.g.Type: GrantFiled: August 10, 2001Date of Patent: November 25, 2003Assignee: Lattice Semiconductor CorporationInventors: Om P. Agrawal, Xiaojie (Warren) He, Claudia A. Stanley, Larry R. Metzger, Chong M. Lee
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Publication number: 20030107401Abstract: An improved, high density CPLD includes a plurality of macrocell sections. Each macrocell section can receive a relatively large number of independent input terms and can generate as a base cluster, at least as many as 5 different product term signals (PT's) therefrom. Part or all of the macrocell's local 5 PT's may be used for generating a local sum-of-products (SoP) signal in a local, first-level ORring operation. Additionally SoP's generated in neighboring macrocell sections may be selectively and incrementally cascaded (cross-laced) for supplemental summing into the local SoP signal. SoP signals of neighboring sections may be further selected in a sums sharing array for second level summing. The combination of the first-level cascading (cross-lacing) and second-level sums sharing provides a wide range of programmably selectable granulations including that of having relatively fast generation of a sum of just a few PT's (e.g.Type: ApplicationFiled: August 10, 2001Publication date: June 12, 2003Applicant: LATTICE SEMICONDUCTOR CORPORATIONInventors: Om P. Agrawal, Xiaojie (Warren) He, Claudia A. Stanley, Larry R. Metzger, Chong M. Lee
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Patent number: 6348813Abstract: An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSM's). An even number of Super Logic Blocks (SLB's) are coupled to each SSM. Each SSM and its SLB's define a segment that couples to the GSM. Each SLB has a relatively large number of inputs (at least 80) and can generate product term signals (PT's) that are products of independent input terms provided from the SSM to the SLB inputs. Some of the product terms generated within each SLB are dedicated to SLB-local controls. Each SLB has at least 32 macrocells and at least 16 I/O pads which feedback to both to the local SSM and the global GSM. 100% intra-segment connectivity is assured within each segment so that each segment can function as an independent, mini-CPLD. Each SSM has additional lines, dedicated for inter-segment (global) communications.Type: GrantFiled: November 22, 2000Date of Patent: February 19, 2002Assignee: Lattice Semiconductor CorporationInventors: Om P. Agrawal, Claudia A. Stanley, Xiaojie (Warren) He, Larry R. Metzger, Robert A. Simon, Kerry A. Ilgenstein
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Patent number: 6184713Abstract: An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSM's). An even number of Super Logic Blocks (SLB's) are coupled to each SSM. Each SSM and its SLB's define a segment that couples to the GSM. Each SLB has a relatively large number of inputs (at least 80) and can generate product term signals (PT's) that are products of independent input terms provided from the SSM to the SLB inputs. Some of the product terms generated within each SLB are dedicated to SLB-local controls. Each SLB has at least 32 macrocells and at least 16 I/O pads which feedback to both to the local SSM and the global GSM. 100% intra-segment connectivity is assured within each segment so that each segment can function as an independent, mini-CPLD. Each SSM has additional lines, dedicated for inter-segment (global) communications.Type: GrantFiled: June 6, 1999Date of Patent: February 6, 2001Assignee: Lattice Semiconductor CorporationInventors: Om P. Agrawal, Claudia A. Stanley, Xiaojie (Warren) He, Larry R. Metzger, Robert A. Simon, Kerry A. Ilgenstein
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Patent number: 6150841Abstract: An improved CPLD includes a plurality of macrocell modules (MM's) where each MM can receive a relatively large number of independent inputs (at least 80) and can generate at least 5 different product term signals (PT's) therefrom. All 5 PT's may be used for generating a local sum-of-products (SoP). Any of the 5 PT's may be stolen (steered-away) to instead provide a local control for its macrocell module. Each module includes a local SoS-producing gate that can produce a sums-of-sums signal (SoS) that represents a Boolean sum of one or more of the local SoP signal, of SoP signals of neighboring macrocell modules, and of SoS signals of neighboring macrocell modules. Simple allocation and super-allocation may be used to produce sums-of-sums signals of relatively large, one-pass function depth, such as 160PT's in one pass.Type: GrantFiled: June 6, 1999Date of Patent: November 21, 2000Assignee: Lattice Semiconductor CorporationInventors: Om P. Agrawal, Claudia A. Stanley, Xiaojie (Warren) He, Chong M. Lee, Robert M. Balzli, Jr., Larry R. Metzger, Kerry A. Ilgenstein