Abstract: Method and apparatus for determining a clock frequency for an electronic processor are provided. One embodiment provides a clock generator for determining a clock frequency for an electronic processor and providing a clock signal to the electronic processor. The clock generator includes a crystal oscillator producing a reference signal and a phase locked loop receiving the reference signal and configured to generate the clock signal based on the reference signal. The clock generator also includes a tuning logic controller electrically coupled to the phase locked loop. The tuning logic controller is configured to program the phase locked loop to a first frequency and determine an integrated circuit process corner of the electronic processor. The tuning logic controller is also configured to determine a second frequency based on the integrated circuit process corner and program the phase locked loop to the second frequency.

Abstract: Method and apparatus for determining a clock frequency for an electronic processor are provided. One embodiment provides a clock generator for determining a clock frequency for an electronic processor and providing a clock signal to the electronic processor. The clock generator includes a crystal oscillator producing a reference signal and a phase locked loop receiving the reference signal and configured to generate the clock signal based on the reference signal. The clock generator also includes a tuning logic controller electrically coupled to the phase locked loop. The tuning logic controller is configured to program the phase locked loop to a first frequency and determine an integrated circuit process corner of the electronic processor. The tuning logic controller is also configured to determine a second frequency based on the integrated circuit process corner and program the phase locked loop to the second frequency.

Abstract: A method and device for generating a multi-rate clock signal using a ring voltage-controlled oscillator based phase-locked loop is provided. The device includes a delay line having a length extending beyond a predetermined length required for operation of the phase-locked loop. The device further includes a tap tuning logic circuit coupled to the delay line. The delay line receives an input signal and a tuning voltage from the phase frequency detector, charge pump and loop filter circuits and generates a plurality of tapped output signals. The plurality of tapped output signals is received by the integrated digital multi-rate clock generator configured to create a plurality of clock signals.

Abstract: A method and apparatus for a method and apparatus for correlation canceller for interference mitigation with adaptive DC offset cancellation for a dual mode communication device includes detecting an active signal transmitting in one mode; configuring integrators associated with the adaptive correlation canceller into gain amplifiers; detecting DC offset utilizing the gain amplifiers and comparators; and configuring the integrators from the gain amplifiers back to integrators with the DC offset applied thereto. The active signal transmitting in one mode can be Long Term Evolution (LTE) which is adjacent to a signal in another mode.

Abstract: A method and apparatus for a method and apparatus for correlation canceller for interference mitigation with adaptive DC offset cancellation for a dual mode communication device includes detecting an active signal transmitting in one mode; configuring integrators associated with the adaptive correlation canceller into gain amplifiers; detecting DC offset utilizing the gain amplifiers and comparators; and configuring the integrators from the gain amplifiers back to integrators with the DC offset applied thereto. The active signal transmitting in one mode can be Long Term Evolution (LTE) which is adjacent to a signal in another mode.

Abstract: A transition control circuit (2) for controlling the transitions of an output signal, at an output node (8) of a driver circuit, in dependence on the logic state of an input signal at an input node (10). The output signal being switchable between a first logic state and a second logic state. The transition control circuit (2) comprises first means (16) and second means (14). The first means (16) is enabled when the output signal has the first logic state and the input signal has the second logic state, and is disabled when the output signal has the second logic state or the input signal has the first logic state. Once enabled, the first means (16) couples the output node (8) to a first supply line (GNDA) whereby the output signal switches to the second logic state. The second means (14) is enabled when the output signal has the second logic state and the input signal has the second logic state, and is disabled when the output signal has the first logic state or the input signal has the first logic state.