Patents by Inventor Claudio Canizares

Claudio Canizares has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136823
    Abstract: A microgrid connector controller (MGC) for transferring power between a power grid and a microgrid via an AC link. The MCG includes a pair of bidirectional AC/DC converters coupled to a common DC link and each having an AC line. One converter closer to the microgrid is configured to regulate frequency of AC voltage of its AC line to a predetermined frequency. The AC link includes the AC lines coupled in series with a terminal the microgrid, and a current divider coupled to a terminal of the power grid. The current divider is configured to set the first converter's current level lower than the second converter's current level.
    Type: Application
    Filed: February 25, 2022
    Publication date: April 25, 2024
    Inventors: Behnam TAMIMI, Claudio CAÑIZARES
  • Patent number: 11075313
    Abstract: A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: July 27, 2021
    Assignee: UTICA LEASECO, LLC
    Inventors: Nikhil Jain, Andrew J. Ritenour, Ileana Rau, Claudio Canizares, Lori D. Washington, Gang He, Brendan M. Kayes
  • Patent number: 10873001
    Abstract: A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: December 22, 2020
    Assignee: ALTA DEVICES, INC.
    Inventors: Nikhil Jain, Andrew J. Ritenour, Ileana Rau, Claudio Canizares, Lori D. Washington, Gang He, Brendan M. Kayes
  • Patent number: 10811557
    Abstract: A growth structure having a lattice transition under a release layer is used as a seed crystal for growth of optoelectronic devices. The optoelectronic device can be a single- or multi-junction photovoltaic device. The release layer can be selectively removed in an epitaxial lift-off (ELO) process to separate the optoelectronic device from the growth structure and leave the region with the lattice transition intact to reuse the growth structure to grow additional devices. A manufacturing method is described that includes providing a growth structure having a substrate and a lattice transition from a first lattice constant to a second lattice constant, depositing a release layer on the growth structure, depositing on the release layer an epitaxial layer having a lattice constant that matches the second lattice and including an optoelectronic device, and removing the release layer to separate the epitaxial layer and the optoelectronic device from the growth structure.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: October 20, 2020
    Assignee: Alta Devices, Inc.
    Inventors: Andrew J. Ritenour, Ileana Rau, Claudio Canizares, Lori D. Washington, Brendan M. Kayes, Gang He
  • Publication number: 20200119216
    Abstract: A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 16, 2020
    Inventors: Nikhil JAIN, Andrew J. RITENOUR, Ileana RAU, Claudio CANIZARES, Lori D. WASHINGTON, Gang HE, Brendan M. KAYES
  • Publication number: 20200119222
    Abstract: A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 16, 2020
    Inventors: Nikhil JAIN, Andrew J. RITENOUR, Ileana RAU, Claudio CANIZARES, Lori D. WASHINGTON, Gang HE, Brendan M. KAYES
  • Publication number: 20180366609
    Abstract: A growth structure having a lattice transition under a release layer is used as a seed crystal for growth of optoelectronic devices. The optoelectronic device can be a single- or multi-junction photovoltaic device. The release layer can be selectively removed in an epitaxial lift-off (ELO) process to separate the optoelectronic device from the growth structure and leave the region with the lattice transition intact to reuse the growth structure to grow additional devices. A manufacturing method is described that includes providing a growth structure having a substrate and a lattice transition from a first lattice constant to a second lattice constant, depositing a release layer on the growth structure, depositing on the release layer an epitaxial layer having a lattice constant that matches the second lattice and including an optoelectronic device, and removing the release layer to separate the epitaxial layer and the optoelectronic device from the growth structure.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 20, 2018
    Inventors: Andrew J. RITENOUR, Ileana RAU, Claudio CANIZARES, Lori D. WASHINGTON, Brendan M. KAYES, Gang He
  • Patent number: 9337377
    Abstract: Atomic layer deposition (ALD) or ALD-like deposition processes are used to fabricate dilute nitride III-V semiconductor materials. A first composition of process gases may be caused to flow into a deposition chamber, and a group V element other than nitrogen and one or more group III elements may be adsorbed over the substrate (in atomic or molecular form). Afterward, a second composition of process gases may be caused to flow into the deposition chamber, and N and one or more group III elements may be adsorbed over the substrate in the deposition chamber. An epitaxial layer of dilute nitride III-V semiconductor material may be formed over the substrate in the deposition chamber from the sequentially adsorbed elements.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: May 10, 2016
    Assignee: SOITEC
    Inventors: Chantal Arena, Robin Scott, Claudio Canizares
  • Patent number: 9324911
    Abstract: Dilute nitride III-V semiconductor materials may be formed by substituting As atoms for some N atoms within a previously formed nitride material to transform at least a portion of the previously formed nitride material into a dilute nitride III-V semiconductor material that includes arsenic. Such methods may be employed in the fabrication of photoactive devices, such as photovoltaic cells and photoemitters. The methods may be carried out within a deposition chamber, such as a metalorganic chemical vapor deposition (MOCVD) or a hydride vapor phase epitaxy (HVPE) chamber.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: April 26, 2016
    Assignee: Soitec
    Inventors: Chantal Arena, Robin Scott, Claudio Canizares
  • Publication number: 20150292088
    Abstract: A deposition system includes two or more gas injectors that may be interchangeably used in a chamber of the deposition system. Each of the gas injectors may be configured to generate a sheet of flowing gas over a substrate support structure. The sheets may have differing widths, such that the gas injectors may be used with substrates having different diameters, which may enable use of the system with different substrates while maintaining efficient use of precursor gas. A method of forming such a deposition system includes forming and configuring such gas injectors to be interchangeably used at a common location within the deposition chamber. A method of using such a deposition system includes using two or more such gas injectors to deposit material on substrates having different sizes.
    Type: Application
    Filed: November 20, 2013
    Publication date: October 15, 2015
    Inventor: Claudio Canizares
  • Publication number: 20150167161
    Abstract: A gas injector includes a base plate, a middle plate, and a top plate. The base plate, middle plate, and top plate are configured to flow a purge gas between the base plate and the middle plate and to flow a precursor gas between the middle plate and the top plate. Another gas injector includes a precursor gas inlet, a lateral precursor gas flow channel, and a plurality of precursor gas flow channels. The plurality of precursor gas flow channels extend from the at least one lateral precursor gas flow channel to an outlet of the gas injector. Methods of forming a material on a substrate include flowing a precursor between a middle plate and a top plate of a gas injector and flowing a purge gas between a base plate and the middle plate of the gas injector.
    Type: Application
    Filed: May 24, 2013
    Publication date: June 18, 2015
    Applicant: Soitec
    Inventors: Claudio Canizares, Dan Gura, Ronald Thomas Bertram, JR.
  • Publication number: 20150128860
    Abstract: Deposition chambers (102) for use with deposition systems (100) include a chamber wall (112) comprising a transparent material. The chamber wall may include an outer metrology window (122) surface extending from and at least partially circumscribed by an outer major surface of the wall, and an inner metrology window surface extending from and at least partially circumscribed by an inner major surface of the wall. The window surfaces may be oriented at angles to the major surfaces. Deposition systems include such chambers. Methods include the formation of such deposition chambers. The depositions systems and chambers may be used to perform in-situ metrology.
    Type: Application
    Filed: May 24, 2013
    Publication date: May 14, 2015
    Applicant: Soitec
    Inventors: Claudio Canizares, Ding Ding
  • Publication number: 20150099065
    Abstract: Visor injectors include a gas injector port, internal sidewalls, and at least two ridges for directing gas flow through the visor injectors. Each of the ridges extends from a location proximate a hole in the gas injector port toward a gas outlet of the visor injector and is positioned between the internal sidewalls. Deposition systems include a base with divergently extending internal sidewalls, a gas injection port, a lid, and at least two divergently extending ridges for directing gas flow through a central region of a space at least partially defined by the internal sidewalls of the base and a bottom surface of the lid. Methods of forming a material on a substrate include flowing a precursor through such a visor injector and directing a portion of the precursor to flow through a central region of the visor injector with at least two ridges.
    Type: Application
    Filed: May 24, 2013
    Publication date: April 9, 2015
    Inventors: Claudio Canizares, Ronald Thomas Bertram, Jr.
  • Publication number: 20130181308
    Abstract: Dilute nitride III-V semiconductor materials may be formed by substituting As atoms for some N atoms within a previously formed nitride material to transform at least a portion of the previously formed nitride into a dilute nitride III-V semiconductor material that includes arsenic. Such methods may be employed in the fabrication of photoactive devices, such as photovoltaic cells and photoemitters. The methods may be carried out within a deposition chamber, such as a metalorganic chemical vapor deposition (MOCVD) or a vapor phase epitaxy (HVPE) chamber.
    Type: Application
    Filed: December 19, 2012
    Publication date: July 18, 2013
    Applicant: Soitec
    Inventors: Chantal Arena, Robin Scott, Claudio Canizares
  • Publication number: 20130164874
    Abstract: Atomic layer deposition (ALD) or ALD-like deposition processes are used to fabricate dilute nitride III-V semiconductor materials. A first composition of process gases may be caused to flow into a deposition chamber, and a group V element other than nitrogen and one or more group III elements may be adsorbed over the substrate (in atomic or molecular form). Afterward, a second composition of process gases may be caused to flow into the deposition chamber, and N and one or more group III elements may be adsorbed over the substrate in the deposition chamber. An epitaxial layer of dilute nitride III-V semiconductor material may be formed over the substrate in the deposition chamber from the sequentially adsorbed elements.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 27, 2013
    Applicant: Soitec
    Inventors: Chantal Arena, Robin Scott, Claudio Canizares
  • Publication number: 20130052333
    Abstract: Deposition systems include a reaction chamber, at least one thermal radiation emitter for heating matter within the reaction chamber, and at least one metrology device for detecting and/or measuring a characteristic of a workpiece substrate in situ within the reaction chamber. One or more chamber walls may be transparent to the thermal radiation and to radiation signals to be received by the metrology device, so as to allow the radiation to pass into and out from the reaction chamber, respectively. At least one volume of opaque material is located to shield a sensor of the metrology device from at least some of the thermal radiation. Methods of forming a deposition system include providing such a volume of opaque material at a location shielding the sensor from the thermal radiation. Methods of using a deposition system include shielding the sensor from at least some of the thermal radiation.
    Type: Application
    Filed: December 15, 2011
    Publication date: February 28, 2013
    Applicant: SOITEC
    Inventors: Ed Lindow, Ronald Bertram, Claudio Canizares