Abstract: A microfluidic device provided in a body accommodating a fluid containment chamber. A fluidic access channel and a drop emission channel are formed in the body and are in fluidic connection with the fluid containment chamber to form a fluidic path towards the body outside through a nozzle having an outlet section. An actuator is operatively coupled to the fluid containment chamber and is configured to cause ejection of fluid drops through the drop emission channel in an operating condition of the microfluidic device. The drop emission channel comprises a portion of reduced section having a smaller area than the outlet section of the nozzle.

Abstract: A microfluidic device provided in a body accommodating a fluid containment chamber. A fluidic access channel and a drop emission channel are formed in the body and are in fluidic connection with the fluid containment chamber to form a fluidic path towards the body outside through a nozzle having an outlet section. An actuator is operatively coupled to the fluid containment chamber and is configured to cause ejection of fluid drops through the drop emission channel in an operating condition of the microfluidic device. The drop emission channel comprises a portion of reduced section having a smaller area than the outlet section of the nozzle.

Abstract: A microfluidic device provided in a body accommodating a fluid containment chamber. A fluidic access channel and a drop emission channel are formed in the body and are in fluidic connection with the fluid containment chamber to form a fluidic path towards the body outside through a nozzle having an outlet section. An actuator is operatively coupled to the fluid containment chamber and is configured to cause ejection of fluid drops through the drop emission channel in an operating condition of the microfluidic device. The drop emission channel comprises a portion of reduced section having a smaller area than the outlet section of the nozzle.

Abstract: A non volatile memory device is integrated on a semiconductor substrate and includes a matrix of memory cells with an associated circuitry. The process for forming the memory device includes forming in the semiconductor substrate first dielectric insulation regions of the matrix to define and insulate first active areas of the matrix from each other, and forming in the semiconductor substrate second dielectric insulation regions of the associated circuitry to define and insulate second active areas of the circuitry from each other. At least one dielectric layer is formed on the first and second active areas. A first conductive layer is deposited on the whole device, and floating gate electrodes of the memory cells of the matrix are defined in the first conductive layer, with the first conductive layer being removed from the associated circuitry.