Abstract: Devices and techniques are disclosed herein to extend a range of an effective delay of a delay circuit having a configurable delay limited to a first range of delay values with respect to a first edge of a clock signal. A selection circuit can selectively apply the configurable delay to a subsequent, second edge of the clock signal to extend the range of the effective delay of the delay circuit beyond the first range of delay values.

Abstract: Apparatus and methods are disclosed, including test systems for memory devices. Example test systems and methods include power loss logic to determine when one or more test conditions have been met in a memory operation between a host device and a memory device under test. Example test systems and methods include a function to then instruct a power management device to trigger a power loss event.

Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

Abstract: Devices and techniques are disclosed herein to extend a range of an effective delay of a delay circuit having a configurable delay limited to a first range of delay values with respect to a first edge of a clock signal. A selection circuit can selectively apply the configurable delay to a subsequent, second edge of the clock signal to extend the range of the effective delay of the delay circuit beyond the first range of delay values.

Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

Abstract: Devices and techniques are disclosed herein for applying an effective sampling delay at a host device to one of an input signal, such as from an embedded MultiMediaCard (eMMC) device, or a clock signal. The host device can apply a configurable delay to one of the input signal or the clock signal with respect to a first edge of the clock signal, sample the input signal using the clock signal according to the configurable delay, and selectively align the sampled input signal to a subsequent, second edge of the clock signal to extend the configurable delay of the host device.

Abstract: Apparatus and methods are disclosed, including test systems for memory devices. Example test systems and methods include power loss logic to determine when one or more test conditions have been met in a memory operation between a host device and a memory device under test. Example test systems and methods include a function to then instruct a power management device to trigger a power loss event.

Abstract: Devices and techniques are disclosed herein for applying an effective sampling delay at a host device to one of an input signal, such as from an embedded MultiMediaCard (eMMC) device, or a clock signal. The host device can apply a configurable delay to one of the input signal or the clock signal with respect to a first edge of the clock signal, sample the input signal using the clock signal according to the configurable delay, and selectively align the sampled input signal to a subsequent, second edge of the clock signal to extend the configurable delay of the host device.

Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

Abstract: Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

Abstract: Various embodiments disclose a controller to manage memory devices. In an exemplary method, signals are exchanged with a host processor to allow the host processor to communicate with multiple memory devices in a memory stack as a single device, regardless of an actual number of memory devices within the memory stack. Power is provided to a single one of the multiple memory devices in the memory stack at a time to reduce power consumption. Other methods, apparatuses, and devices are also disclosed.

Abstract: A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack.

Abstract: Various embodiments disclose a controller to manage memory devices. In an exemplary method, signals are exchanged with a host processor to allow the host processor to communicate with a plurality of memory devices in a memory stack as a single device, regardless of an actual number of memory devices within the memory stack. Power is provided to a single one of the plurality of the memory devices in the memory stack at a time to reduce power consumption. Other methods, apparatuses, and devices are also disclosed.

Abstract: A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack.

Abstract: In various embodiments, a single virtualized error correcting code (ECC) NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack. In various embodiments, a controller manages a plurality of NAND memory devices. The controller provides power to a select one of the plurality of NAND memory devices at a time to conserve overall power consumption of the storage system.

Abstract: In various embodiments, a single virtualized error correcting code (ECC) NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack. In various embodiments, a controller manages a plurality of NAND memory devices. The controller provides power to a select one of the plurality of NAND memory devices at a time to conserve overall power consumption of the storage system.

Abstract: A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack.