Abstract: A method for estimating a time-of-arrival of a packet received by a receiver includes storing a reference bit-pattern and receiving a plurality of samples in a samples-buffer. In a bit-pattern detector, a matching group of samples having a bit-pattern which matches the reference bit-pattern is identified. In a correlator, a group of three correlation values is determined from the matching group of samples, including a local maximum correlation value, P0, an immediately preceding correlation value, Pm, and an immediately succeeding correlation value Pp. In an estimation unit, a polynomial function f(?) of the difference, ?, between Pm and Pp is used to estimate a timing offset Tfrac, between the local maximum correlation value and a correlation peak. The time-of-arrival is estimated from a time of the local maximum correlation value P0, and Tfrac.

Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (??LO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.

Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (??LO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.

Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. A first frequency and first relative phase of a first output signal are locked to a frequency and a phase of a first input signal. A second frequency and second relative phase of a second output signal are locked to a frequency and a phase of a second input signal. A correction to the PLL is applied to perform one of: adjusting the second relative phase to equal the first relative phase and adjusting the oscillator frequency.

Abstract: A method for estimating a time-of-arrival of a packet received by a receiver includes storing a reference bit-pattern and receiving a plurality of samples in a samples-buffer. In a bit-pattern detector, a matching group of samples having a bit-pattern which matches the reference bit-pattern is identified. In a correlator, a group of three correlation values is determined from the matching group of samples, including a local maximum correlation value, P0, an immediately preceding correlation value, Pm, and an immediately succeeding correlation value Pp. In an estimation unit, a polynomial function f(?) of the difference, ?, between Pm and Pp is used to estimate a timing offset Tfrac, between the local maximum correlation value and a correlation peak. The time-of-arrival is estimated from a time of the local maximum correlation value P0, and Tfrac.

Abstract: An acquisition detector and method include a preamble detector configured to search in a plurality of symbols for a preamble match with a known preamble pattern when a power level of the input signal exceeds a determined noise threshold. The acquisition detector further includes a frame delimiter detector configured to search in the plurality of symbols for a frame delimiter match with a known frame delimiter pattern when the preamble match is identified and the power level of the input signal exceeds a determined noise threshold.

Abstract: The embodiments described herein provide systems and methods for digital correction in low intermediate frequency (IF) receivers. Specifically, the embodiments described herein use digital correction techniques that can correct for signal distortions in low IF receivers caused by I-Q imbalance, including both I-Q magnitude imbalance and I-Q phase imbalance. In general, the embodiments described herein are implemented to at least partially cancel an image of a blocking signal in the complex digital signal. Such a cancellation can be implemented to at least partially cancel an image of blocking signal where that image occurs at or near the intermediate frequency. In one embodiment, a corrector is implemented in a low RF receiver and is configured to receive a complex digital signal that includes an image of a blocking signal. Such a low RF receiver can further include a corrector controller to selectively enable the corrector.

Abstract: An arbitrary rate digital decimator filter (204) and associated method are disclosed for filtering a digital data stream with a plurality of cascaded power-of-two decimator stages (205, 207) connected to receive the digital data stream and to generate a first filtered digital signal which is provided to a fractional resampling stage (211) which generates a second filtered digital signal with delta-sigma modulator (310) and a limited integrator stage (320) connected to receive a first control (301) word and a feedback clock signal (305) with inserted or swallowed pulses which is generated by a clock generator in response to pulse commands generated by the limited integrator stage, wherein the limited integrator is configured to generate time shift commands (303) to a timing shift filter (340) which performs fractional interpolation on the first filtered digital signal to generate the second filtered digital signal.

Abstract: The embodiments described herein provide systems and methods for digital correction in low intermediate frequency (IF) receivers. Specifically, the embodiments described herein use digital correction techniques that can correct for signal distortions in low IF receivers caused by I-Q imbalance, including both I-Q magnitude imbalance and I-Q phase imbalance. In general, the embodiments described herein are implemented to at least partially cancel an image of a blocking signal in the complex digital signal. Such a cancellation can be implemented to at least partially cancel an image of blocking signal where that image occurs at or near the intermediate frequency. In one embodiment, a corrector is implemented in a low RF receiver and is configured to receive a complex digital signal that includes an image of a blocking signal. Such a low RF receiver can further include a trainer configured to train the corrector to generate the cancellation signal.

Abstract: An acquisition detector and method include a preamble detector configured to search in a plurality of symbols for a preamble match with a known preamble pattern when a power level of the input signal exceeds a determined noise threshold. The acquisition detector further includes a frame delimiter detector configured to search in the plurality of symbols for a frame delimiter match with a known frame delimiter pattern when the preamble match is identified and the power level of the input signal exceeds a determined noise threshold.

Abstract: A demodulator and method includes a plurality of correlation circuits, a result combining stage, and a time combining stage. The plurality of correlation circuits may be configured to output a plurality of correlation values that indicate a likelihood of whether a pattern of a buffered portion of an input data signal matches a first plurality of target frequency behavior patterns. The plurality of correlation circuits may be further configured to output a plurality of delayed correlation values that indicate a likelihood of whether a pattern of a delayed buffered portion of the input data signal matches a second plurality of target frequency behavior patterns, where both the buffered portion and the delayed buffered portion include a current symbol.

Abstract: A preamble detection system and method includes converting the phase domain input samples corresponding to the preamble into frequency domain input samples. An I/Q-formatted dot product is generated from a dot product process between the frequency domain input samples and a reference pattern indicative of an expected preamble. The I/Q-formatted dot product is averaged with at least one previously generated I/Q-formatted dot product to generate an I/Q-formatted averaged dot product. The I/Q-formatted averaged dot product is converted into a polar-formatted averaged dot product, wherein the polar-formatted averaged dot product includes a magnitude of the polar-formatted averaged dot product and an angle of the polar-formatted averaged dot product. A preamble-found signal is then generated in response to the magnitude of the polar-formatted averaged dot product exceeding a preamble magnitude threshold.

Abstract: A demodulator and method includes a plurality of correlation circuits, a result combining stage, and a time combining stage. The plurality of correlation circuits may be configured to output a plurality of correlation values that indicate a likelihood of whether a pattern of a buffered portion of an input data signal matches a first plurality of target frequency behavior patterns. The plurality of correlation circuits may be further configured to output a plurality of delayed correlation values that indicate a likelihood of whether a pattern of a delayed buffered portion of the input data signal matches a second plurality of target frequency behavior patterns, where both the buffered portion and the delayed buffered portion include a current symbol.

Abstract: A method includes, at a frequency shift keying (FSK) demodulator, determining a likelihood of a symbol having a first symbol value or a second symbol value, using the likelihood of the symbol to select either the first symbol value or the second symbol value for the symbol, the first symbol value or the second symbol value that is selected being a selected symbol value, selecting a frequency error from a first frequency error or a second frequency error, and using a down-mixer and the frequency error to correct a frequency drift associated with a future selected symbol value.

Abstract: A method includes, at a frequency shift keying (FSK) demodulator, determining a likelihood of a symbol having a first symbol value or a second symbol value, using the likelihood of the symbol to select either the first symbol value or the second symbol value for the symbol, the first symbol value or the second symbol value that is selected being a selected symbol value, selecting a frequency error from a first frequency error or a second frequency error, and using a down-mixer and the frequency error to correct a frequency drift associated with a future selected symbol value.

Abstract: A frame delimiter detection system and method includes a phase differentiator and buffering module, a phase-to-I/Q reformatting module, a dot product module, an I/Q-to-polar reformatting module, a dot product comparison module, and a frame delimiter detection module. The method may include receiving in-phase and quadrature-phase (I/Q) formatted frequency domain input samples configured as a frame delimiter in a communication packet. An I/Q formatted dot product may be generated from the I/Q formatted frequency domain input samples and a reference pattern indicative of an expected frame delimiter. Further, a frame delimiter detection signal may be generated based on a magnitude of the I/Q formatted dot product.

Abstract: The invention provides a synchronizer incorporating a ?-? modulator (i.e. a bit stuffing command generator), coupled in series with a frequency offset measurement block and a frequency-locked loop, to synchronize the data rate of an output data stream to that of an input data stream such that jitter energy is shifted up in frequency, simplifying attenuation of the jitter energy when the output data stream is desynchronized (demapped). Placement of the ?-? modulator outside the frequency-locked loop allows selectable adjustment of the frequency offset measurement block's frequency. A mapper incorporating the ?-? modulator interprets the pulse train output by the ?-? modulator as stuff/null/de-stuff commands.

Abstract: An equalizer for return-to-zero (RZ) signals comprises: (a) an equalizer core for equalizing the received signal; (b) a decision corrector for detecting and correcting misplaced pulses and double pulses in the equalized signal using known characteristics and properties of the RZ signal itself; and (c) an error calculator that generates an error signal for updating tap values based on the initial outputs of the equalizer core and the corrected outputs of the decision corrector. The decision corrector comprises a zero assertion counter that generates a clock synchronized with the timing of the received signal, and corrects the equalized signal by forcing zeroes in those portions of the equalized signal that the synchronized clock indicates should be “RZ” zeroes (as opposed to “data” zeroes or “data” symbols “1” or “?1”).

Abstract: An apparatus and method for jointly equalizing a return to zero (RZ) signal and detecting timing errors in the RZ signal, using values or indices from equalizer taps, including a set reference tap that does not shift. A timing error detector detects a timing error based on a group delay measured from the equalizer tap information, and then adjustment circuitry modifies samples of the received RZ signal prior to their equalization to offset that timing error. Methods of modifying the samples to offset the timing error include adjusting the timing of the sampler, or adjusting the sampled data using intermediate, interpolated samples generated by a timing interpolation filter.

Abstract: A physical channel estimator for a communication system using pilot symbols and an equalizer uses a model of the system in which the impulse response of the physical channel is considered separately from the impulse responses of the pulse shaping filters in the transmitter and receiver of the communication system. The system is modeled as if the signals were propagated first through both pulse shaping filters and then through the physical channel. To estimate the physical channel impulse response, known pilot symbols are transmitted and then sampled. The pilot symbol samples and the known impulse responses of the pulse shaping filters are then used to estimate the physical channel impulse response. In one embodiment, the physical channel impulse response is considered time-invariant over the estimation period and a sufficient number of pilot symbol samples are taken so that the system is overdetermined.