Abstract: A CDS device of an image sensor having a pixel array includes first comparators, second comparators and third comparators. The first comparators are coupled to columns of the pixel array, and generate a positive amplified signal and a negative amplified signal by comparing the analog signal and a ramp signal. The second comparators are coupled to a first set of the first comparators coupled to first columns of the pixel array, and generate a first comparison signal enabled to a first logic level by comparing the positive amplified signal and the negative amplified signal. The third comparators are coupled to a second set of the first comparators coupled to second columns of the pixel array, and generate a second comparison signal enabled to a second logic level by comparing the positive amplified signal and the negative amplified signal.

Abstract: A correlated double sampling circuit includes a first input terminal receiving a ramp signal having first and second ramp sections, a second input terminal receiving a pixel signal, and a comparing circuit comparing the ramp signal with the pixel signal to generate an output signal, wherein the comparing circuit changes a point in time at which the output signal logically transitions during the first ramp section and the second ramp section in response to an applied dithering enable signal.

Abstract: A correlated double sampling circuit includes a first input terminal receiving a ramp signal having first and second ramp sections, a second input terminal receiving a pixel signal, and a comparing circuit comparing the ramp signal with the pixel signal to generate an output signal, wherein the comparing circuit changes a point in time at which the output signal logically transitions during the first ramp section and the second ramp section in response to an applied dithering enable signal.

Abstract: A CDS device of an image sensor having a pixel array includes first comparators, second comparators and third comparators. The first comparators are coupled to columns of the pixel array, and generate a positive amplified signal and a negative amplified signal by comparing the analog signal and a ramp signal. The second comparators are coupled to a first set of the first comparators coupled to first columns of the pixel array, and generate a first comparison signal enabled to a first logic level by comparing the positive amplified signal and the negative amplified signal. The third comparators are coupled to a second set of the first comparators coupled to second columns of the pixel array, and generate a second comparison signal enabled to a second logic level by comparing the positive amplified signal and the negative amplified signal.