Abstract: A wireless telephone includes first and second baseband processors. The first baseband processor functions as system master, and the second processor functions as system slave. The first baseband processor interfaces to system controls, such as power supply, man-machine interface (MMI), and the like. The master processor implements a first pair of buffers in the downlink direction and a second pair in an uplink direction. The buffers in the pairs are swapped periodically, based on an internal counter running on the master processor. The timing of the master processor is continuously adjusted to that of the slaved co-processor, by counting a number of samples received from the microphone respectively fed to the earpiece between the beginning of consecutive frames. The timing of the master processor is then adjusted accordingly. The output of the counter may be lowpass filtered to separate jitter from frequency deviation.

Abstract: A wireless telephone includes first and second baseband processors. The first baseband processor functions as system master, and the second processor functions as system slave. The first baseband processor interfaces to system controls, such as power supply, man-machine interface (MMI), and the like. The master processor implements a first pair of buffers in the downlink direction and a second pair in an uplink direction. The buffers in the pairs are swapped periodically, based on an internal counter running on the master processor. The timing of the master processor is continuously adjusted to that of the slaved co-processor, by counting a number of samples received from the microphone respectively fed to the earpiece between the beginning of consecutive frames. The timing of the master processor is then adjusted accordingly. The output of the counter may be lowpass filtered to separate jitter from frequency deviation.