Abstract: A transceiver system compensates for baseline wandering in an analog signal in the analog stage before sampling the analog signal and processing the analog signal in the digital stage. The transceiver system includes an analog to digital converter that samples the analog signal after baseline wandering compensation, a digital equalizer to condition the digital samples, and the slicer to determine transmitted symbols from the digital samples. The transceiver system includes a subtraction block that determines the difference between an input and an output of the slicer, a digital to analog converter that converts a difference between the input and the output of the slicer, a low pass filter that filters out high frequency components of the difference between the input and the output of the slicer thereby to extract out the baseline wandering, and a signal summation circuit that subtracts the baseline wandering from the analog signal.

Abstract: A receiver system that includes an ADC for converting analog values to digital representations. A digital representation is a sum of discrete values some of which are non-binary scaled and the other are binary scaled. The ADC includes dedicated comparators to determine whether to add or to subtract the non-binary scaled values. A comparator is used to determine whether to add or to subtract the binary scaled values. The ADC further calibrates offset voltages of the comparators to substantially remove dead zone and conversion errors, without compromising the conversion speed. The calibration can be performed both in foreground and background.

Abstract: A receiver system that includes an ADC for converting analog values to digital representations. A digital representation is a sum of discrete values some of which are non-binary scaled and the other are binary scaled. The ADC includes dedicated comparators to determine whether to add or to subtract the non-binary scaled values. A comparator is used to determine whether to add or to subtract the binary scaled values. The ADC further calibrates offset voltages of the comparators to substantially remove dead zone and conversion errors, without compromising the conversion speed. The calibration can be performed both in foreground and background.

Abstract: A hybrid digital-to-analog converter including a charge-sharing digital-to-analog converter and a charge redistribution digital-to-analog converter is provided. The charge-sharing digital-to-analog converter is configured to receive a digital input signal having multiple bits. The bits include a most-significant-bit and a least-significant-bit. The charge-sharing digital-to-analog converter is configured to convert the most-significant-bit to provide a first portion of an analog signal and selectively share charges of first capacitors during a successive approximation of the most-significant-bit. The charge redistribution digital-to-analog converter is configured to convert the least-significant-bit to provide a second portion of the analog signal. The charge redistribution digital-to-analog converter performs charge redistribution by selectively connecting second capacitors to receive reference voltages during a successive approximation of the least-significant-bit.

Abstract: A hybrid digital-to-analog converter including a charge-sharing digital-to-analog converter and a charge redistribution digital-to-analog converter is provided. The charge-sharing digital-to-analog converter is configured to receive a digital input signal having multiple bits. The bits include a most-significant-bit and a least-significant-bit. The charge-sharing digital-to-analog converter is configured to convert the most-significant-bit to provide a first portion of an analog signal and selectively share charges of first capacitors during a successive approximation of the most-significant-bit. The charge redistribution digital-to-analog converter is configured to convert the least-significant-bit to provide a second portion of the analog signal. The charge redistribution digital-to-analog converter performs charge redistribution by selectively connecting second capacitors to receive reference voltages during a successive approximation of the least-significant-bit.

Abstract: An A/D converter including first and second A/D converters and a recombination module. The first A/D converter receives an analog input signal, converts the analog input signal to a first digital signal, and includes a successive approximation module, which performs a successive approximation to generate the first digital signal. The second A/D converter converts an analog output of the first A/D converter to a second digital signal. The analog output of the first A/D converter is generated based on the analog input signal. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter. The second A/D converter performs the delta-sigma conversion process and includes a decimation filter that suppresses noise which reduces amplification and power consumption requirements of the first A/D converter and performs a delta-sigma decimation process to generate the second digital signal based on the analog output of the first A/D converter.

Abstract: A hybrid D/A converter is provided including first and second D/A converters. The first D/A converter receives a digital signal having an input voltage and converts a first most-significant-bit of the digital signal to be converted to an analog signal. The first D/A converter includes first capacitors, which are charged by the input voltage and reference voltages during a sampling phase of the digital signal. Charges of the first capacitors are shared during successive approximations of first bits of the digital input signal received by the hybrid D/A converter. The second D/A converter converts a first least-significant-bit of the digital input signal. The second D/A converter includes second capacitors, which are charged based on a common mode voltage during the sampling phase. The second D/A converter performs charge redistribution by connecting the second capacitors to receive the reference voltages during successive approximations of second bits of the digital signal.

Abstract: An A/D converter including a sample and hold circuit, first and second A/D converters and a combination circuit. The sample and hold circuit samples an analog input signal to generate bits. The first A/D converter generate a first digital signal based on the analog input signal and includes charge-sharing and charge-redistribution D/A converters that convert respectively a most-significant-bit and a first least significant bit. The first digital signal is generated based on outputs of the charge-sharing and charge redistribution D/A converters. The second A/D converter generates a second digital signal based on an output of the first A/D converter and includes a delta sigma D/A converter, which converts a second least significant bit. The second digital signal is generated based on an output of the delta sigma D/A converter. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter.

Abstract: A hybrid D/A converter is provided including first and second D/A converters. The first D/A converter receives a digital signal having an input voltage and converts a first most-significant-bit of the digital signal to be converted to an analog signal. The first D/A converter includes first capacitors, which are charged by the input voltage and reference voltages during a sampling phase of the digital signal. Charges of the first capacitors are shared during successive approximations of first bits of the digital input signal received by the hybrid D/A converter. The second D/A converter converts a first least-significant-bit of the digital input signal. The second D/A converter includes second capacitors, which are charged based on a common mode voltage during the sampling phase. The second D/A converter performs charge redistribution by connecting the second capacitors to receive the reference voltages during successive approximations of second bits of the digital signal.

Abstract: An A/D converter including first and second A/D converters and a recombination module. The first A/D converter receives an analog input signal, converts the analog input signal to a first digital signal, and includes a successive approximation module, which performs a successive approximation to generate the first digital signal. The second A/D converter converts an analog output of the first A/D converter to a second digital signal. The analog output of the first A/D converter is generated based on the analog input signal. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter. The second A/D converter performs the delta-sigma conversion process and includes a decimation filter that suppresses noise which reduces amplification and power consumption requirements of the first A/D converter and performs a delta-sigma decimation process to generate the second digital signal based on the analog output of the first A/D converter.

Abstract: An A/D converter including a sample and hold circuit, first and second A/D converters and a combination circuit. The sample and hold circuit samples an analog input signal to generate bits. The first A/D converter generate a first digital signal based on the analog input signal and includes charge-sharing and charge-redistribution D/A converters that convert respectively a most-significant-bit and a first least significant bit. The first digital signal is generated based on outputs of the charge-sharing and charge redistribution D/A converters. The second A/D converter generates a second digital signal based on an output of the first A/D converter and includes a delta sigma D/A converter, which converts a second least significant bit. The second digital signal is generated based on an output of the delta sigma D/A converter. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter.

Abstract: A non-binary successive approximation analogue to digital converter, for converting using successive conversion steps, is operable in first and second modes. The first and second modes have different noise properties and the converter is switched between the modes during the conversion process.

Abstract: A non-binary successive approximation analogue to digital converter, for converting using successive conversion steps, is operable in first and second modes. The first and second modes have different noise properties and the converter is switched between the modes during the conversion process.