Patents by Inventor Claudio Pinello

Claudio Pinello has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11544931
    Abstract: An analytics device for monitoring maintenance on an elevator system performed by an individual including: a processor; and a memory including computer-executable instructions that, when executed by the processor, cause the processor to perform operations, the operations including: capturing a first video stream using a first video camera; extracting sequences from at least the first video stream; extracting features from the sequences; and analyzing, using a long short-term memory model, the sequence to determine whether the maintenance performed on the elevator system by the individual is performed correctly.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: January 3, 2023
    Assignee: OTIS ELEVATOR COMPANY
    Inventors: Amit Bhatia, Guoqiang Wang, Mahmoud El Chamie, Claudio Pinello, Ankit Tiwari, Massimiliano L. Chiodo
  • Publication number: 20210374424
    Abstract: An analytics device for monitoring maintenance on an elevator system performed by an individual including: a processor; and a memory including computer-executable instructions that, when executed by the processor, cause the processor to perform operations, the operations including: capturing a first video stream using a first video camera; extracting sequences from at least the first video stream; extracting features from the sequences; and analyzing, using a long short-term memory model, the sequence to determine whether the maintenance performed on the elevator system by the individual is performed correctly.
    Type: Application
    Filed: November 20, 2020
    Publication date: December 2, 2021
    Inventors: Amit Bhatia, Guoqiang Wang, Mahmoud El Chamie, Claudio Pinello, Ankit Tiwari, Massimiliano L. Chiodo
  • Patent number: 8341567
    Abstract: A method is provided to formally verify a property of a circuit design comprising: receiving a description of at least a portion of the circuit; receiving an indication of search accuracy criteria; receiving a description of a relationship between current and voltage (I-V relationship) for one or more of devices of the circuit; converting each I-V relationship to a conservative approximation of such I-V relationship; assigning voltage labels to one or more terminals of one or more identified devices that indicate voltage relationships among the one or more terminals consistent with KVL; defining a respective current relationship among one or more respective sets of currents of the one or more of the identified devices that is consistent with KCL; searching for one or more combinations of current and voltage values that are within at least one region of each conservative approximation and that are consistent with the voltage labels and that are consistent with each respective defined current relationship; conv
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: December 25, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips, Claudio Pinello, Radu Zlatanovici