Abstract: A wireless device includes a receiver to receive a packet via one or more antennas. A frame synchronization detection circuit coupled to the receiver identifies a frame synchronization pattern within a portion of the packet. A correlation circuit coupled to the frame synchronization detection circuit computes one or more values of a correlation peak using a correlation method. A fractional timing approximation circuit coupled to the correlation circuit determines a pulse shape using the one or more values of the correlation peak; and determines a fractional timing approximation for the packet using the pulse shape.

Abstract: A wireless device includes a transmitter adapted with Bluetooth® low energy (BLE) capability and logic at least one of coupled to or integrated within the transmitter. The logic randomly generates a frequency offset based on bits within a frame synch packet to be transmitted during a keyless access attempt of an enclosure having a receiver. The logic causes the bits of the frame synch packet to be encrypted with an encryption key. The logic causes a frequency of the frame synch packet to modified by the frequency offset before the transmitter transmits the frame synch packet to the receiver.

Abstract: A device includes a receiver to receive a packet over a channel at a first frequency and generate a sampled stream of data at a first sample rate corresponding to the first frequency. A data resampler circuit includes a re-timer engine to determine, using a fractional rate between the first sample rate and a crystal oscillator (XO)-divided sample rate, re-timer values including a difference between pulses of a pseudo clock corresponding to the XO-integer-divided sample rate and closest corresponding pulses of a clock corresponding to the first sample rate. The data resampler circuit includes a time shifting circuit to re-sample data values of the sampled stream of data associated with locations of the plurality of re-timer values. A correlation circuit uses the re-sampled data values, pseudo clock, and the re-timer values to match an expected data pattern to a corresponding data pattern detected in a frame delimiter of the packet.

Abstract: A device includes a receiver to receive a packet over a channel at a first frequency and generate a sampled stream of data at a first sample rate corresponding to the first frequency. A data resampler circuit includes a re-timer engine to determine, using a fractional rate between the first sample rate and a crystal oscillator (XO)-divided sample rate, re-timer values including a difference between pulses of a pseudo clock corresponding to the XO-integer-divided sample rate and closest corresponding pulses of a clock corresponding to the first sample rate. The data resampler circuit includes a time shifting circuit to re-sample data values of the sampled stream of data associated with locations of the plurality of re-timer values. A correlation circuit uses the re-sampled data values, pseudo clock, and the re-timer values to match an expected data pattern to a corresponding data pattern detected in a frame delimiter of the packet.

Abstract: Techniques described here introduce signature frequency modulation to unmodulated pulse signals as frequency chirps to enhance the security of multi-carrier phase-based ranging signals. The characteristics of the chirps may be mutually known by an initiator and a desired reflector of the ranging applications. The characteristics of the chirps may vary between the multi-carrier signals to thwart any attempt by an eavesdropper to predict the chirps. In one aspect, the characteristics of the chirps may be calculated for each timeslot of a ranging cycle by two authorized devices using a ciphering algorithm such as the Advanced Encryption Standard (AES) based on a shared security key. Each call of the AES may generate one or more pseudo-random numbers based on the shared security key and a time-varying initialization vector that increments every timeslot. Fields of the pseudo-random number may be extracted to determine the characteristics of the chirps associated with the timeslot.

Abstract: A wireless device includes a receiver to receive a packet via one or more antennas. A frame synchronization detection circuit coupled to the receiver identifies a frame synchronization pattern within a portion of the packet. A correlation circuit coupled to the frame synchronization detection circuit computes, in response to the identifying of the frame synchronization pattern within the portion of the packet, a frequency offset using a correlation method. A frequency estimation correction circuit coupled to the correlation circuit determines, based on the frame synchronization pattern, a bias value, wherein the bias value corresponds to a data pattern within the frame synchronization pattern indicative of a frequency bias, and applies a correction to the frequency offset, wherein applying the correction to the frequency offset comprises modifying the frequency offset using the bias value.

Abstract: Techniques are described to improve the security of frame synchronization detection between wireless devices in high accuracy positioning (HAP) applications using personal area networks (PANs). A receiver may detect whether a frame synchronization pattern has been manipulated by comparing the sampled data of the received frame synchronization pattern with a reference waveform predicted as the frame synchronization pattern. The receiver may reuse the data in the correlation buffer at the moment a correlator finds a peak and declares that the synchronization pattern is found. The correlator may also provide fractional timing information associated with the correlation peak for the receiver to create a delayed reference phase differential pattern. The receiver may subtract the data in the correlation buffer by the delayed reference differential data and look for absolute deviations in the output of such subtraction that exceed a predetermined threshold.

Abstract: A method of operating frequency shift keying (FSK) demodulator for demodulating symbols includes providing current and previous buffered portions of an input signal to correlation circuits of the FSK demodulator, where each buffered portion persists for a symbol duration time period. The correlation circuits output first correlation metrics that indicate a likelihood of whether the buffered portions match a respective target pattern. The first correlation metrics are combined into a set of first correlation results, which are delayed by at least the symbol duration time period. The current and next buffered portions are provided to the correlation circuits, which output second correlation metrics that are combined into a set of second correlation results. The set of second correlation results are combined with the delayed set of first correlation results to produce a demodulation decision that indicates a most likely symbol value encoded in the current buffered portion.

Abstract: A method of operating frequency shift keying (FSK) demodulator for demodulating symbols includes providing current and previous buffered portions of an input signal to correlation circuits of the FSK demodulator, where each buffered portion persists for a symbol duration time period. The correlation circuits output first correlation metrics that indicate a likelihood of whether the buffered portions match a respective target pattern. The first correlation metrics are combined into a set of first correlation results, which are delayed by at least the symbol duration time period. The current and next buffered portions are provided to the correlation circuits, which output second correlation metrics that are combined into a set of second correlation results. The set of second correlation results are combined with the delayed set of first correlation results to produce a demodulation decision that indicates a most likely symbol value encoded in the current buffered portion.

Abstract: A method and apparatus for identifying a search window of carrier-frequency-offset-corrected samples in which a first intermediate signal from a demodulator does not exceed a predetermined threshold, convolving a second intermediate signal from the demodulator within the search window with a predefined pattern to provide a convolution result, determining if an absolute peak of the convolution result exceeds a preamble pattern confirmation threshold, in response to the absolute peak of the convolution result exceeding the preamble confirmation threshold, confirming a preamble pattern detection event to provide a confirmed preamble pattern detection event of a confirmed preamble pattern, and receiving a signal including the confirmed preamble pattern to provide a received digital signal extracted from the signal.

Abstract: A frequency shift keying (FSK) demodulator for demodulating symbols includes correlation circuits configured to output correlation metrics based on a buffered portion of an input signal as the input signal is continuously received by the FSK demodulator. The FSK demodulator also includes a result combining stage configured to output a set of first correlation results based on correlation metrics generated for a first portion of the input signal encoding a current symbol and at least one past symbol, and a set of second correlation results based on correlation metrics generated for a second portion of the input signal encoding the current symbol and at least one next symbol; and a time combining stage configured to combine a set of delayed first correlation results with the set of second correlation results to produce a demodulation decision that returns a most likely symbol value for the current symbol.

Abstract: A circuit may include a digitally-controlled oscillator including a coarse frequency-tuning array with a multiple selectable coarse frequency-tuning segments. Each of the coarse frequency-tuning segments may have a coarse segment frequency step size. The digitally-controlled oscillator may also include a fine frequency-tuning array with multiple selectable fine frequency-tuning segments. The fine frequency-tuning array may have a fine array frequency step size that is at least twice the coarse segment frequency step size. The digitally-controlled oscillator may be configured to generate an output signal with a frequency based on the coarse frequency-tuning array and the fine frequency-tuning array.

Abstract: A method of generating a transmission signal may include mixing a baseband signal assigned for transmission within a narrow frequency range (“assigned narrow frequency range”) included in a wireless communication channel to produce a shifted signal. The shifted signal may have a shifted frequency that is based on a shift from the assigned narrow frequency range toward a center frequency of the wireless communication channel by a frequency offset. The method may further include shifting a modulation frequency of a modulating signal toward the assigned narrow frequency range frequency range and away from the center frequency by the frequency offset. Additionally, the method may include mixing the shifted signal with the modulating signal to produce a transmission signal having a transmission frequency within the assigned narrow frequency range.

Abstract: In accordance with some embodiments of the present disclosure, a method may include determining a range of frequencies allocated to resource blocks to be transmitted during a subsequent sub-frame slot or sounding reference symbol sub-slot. The method may also include determining an approximate center frequency of the range of frequencies. The method may additionally include modulating resource blocks of the sub-frame or sounding reference symbol sub-slot at the approximate center frequency. The method may further include transmitting the modulated resource blocks at the approximate center frequency.

Abstract: A circuit may include an oscillator configured to generate an output signal based on an analog signal and a digital signal and a controller configured to generate an offset signal based on a comparison of a first analog control signal and a second analog control signal. The circuit may also include a divider configured to generate a feedback signal based on the output signal and the offset signal. The circuit may also include an analog control signal unit configured to generate the second analog control signal based on the feedback signal and a reference signal and a coupling unit configured to select either the first analog control signal or the second analog control signal as the analog signal.

Abstract: A method of generating a transmission signal may include mixing a baseband signal assigned for transmission within a narrow frequency range (“assigned narrow frequency range”) included in a wireless communication channel to produce a shifted signal. The shifted signal may have a shifted frequency that is based on a shift from the assigned narrow frequency range toward a center frequency of the wireless communication channel by a frequency offset. The method may further include shifting a modulation frequency of a modulating signal toward the assigned narrow frequency range frequency range and away from the center frequency by the frequency offset. Additionally, the method may include mixing the shifted signal with the modulating signal to produce a transmission signal having a transmission frequency within the assigned narrow frequency range.

Abstract: A circuit may include an oscillator configured to generate an output signal based on an analog signal and a digital signal and a controller configured to generate an offset signal based on a comparison of a first analog control signal and a second analog control signal. The circuit may also include a divider configured to generate a feedback signal based on the output signal and the offset signal. The circuit may also include an analog control signal unit configured to generate the second analog control signal based on the feedback signal and a reference signal and a coupling unit configured to select either the first analog control signal or the second analog control signal as the analog signal.

Abstract: A circuit may include a digitally-controlled oscillator including a coarse frequency-tuning array with a multiple selectable coarse frequency-tuning segments. Each of the coarse frequency-tuning segments may have a coarse segment frequency step size. The digitally-controlled oscillator may also include a fine frequency-tuning array with multiple selectable fine frequency-tuning segments. The fine frequency-tuning array may have a fine array frequency step size that is at least twice the coarse segment frequency step size. The digitally-controlled oscillator may be configured to generate an output signal with a frequency based on the coarse frequency-tuning array and the fine frequency-tuning array.

Abstract: A circuit may include a phase detector configured to generate a phase error signal based on a feedback signal and an oscillator configured to generate an output signal. The feedback signal may be based on the output signal. The circuit may also include a determination unit configured to measure a phase of the feedback signal based on the phase error signal when an output of the phase detector and an input of the oscillator are communicatively decoupled. The circuit may also include an adjustment unit configured to subtract the measured phase of the feedback signal from an intermediate signal upon which the output signal is based when the output of the phase detector and the input of the oscillator are communicatively coupled.

Abstract: A circuit may include a phase detector configured to generate a phase error signal based on a feedback signal and an oscillator configured to generate an output signal. The feedback signal may be based on the output signal. The circuit may also include a determination unit configured to measure a phase of the feedback signal based on the phase error signal when an output of the phase detector and an input of the oscillator are communicatively decoupled. The circuit may also include an adjustment unit configured to subtract the measured phase of the feedback signal from an intermediate signal upon which the output signal is based when the output of the phase detector and the input of the oscillator are communicatively coupled.