Patents by Inventor Claudionor Jose Nunes Coelho
Claudionor Jose Nunes Coelho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230229895Abstract: Systems and methods for producing a neural network architecture with improved energy consumption and performance tradeoffs are disclosed, such as would be deployed for use on mobile or other resource-constrained devices. In particular, the present disclosure provides systems and methods for searching a network search space for joint optimization of a size of a layer of a reference neural network model (e.g., the number of filters in a convolutional layer or the number of output units in a dense layer) and of the quantization of values within the layer. By defining the search space to correspond to the architecture of a reference neural network model, examples of the disclosed network architecture search can optimize models of arbitrary complexity. The resulting neural network models are able to be run using relatively fewer computing resources (e.g., less processing power, less memory usage, less power consumption, etc.), all while remaining competitive with or even exceeding the performance (e.g.Type: ApplicationFiled: June 2, 2021Publication date: July 20, 2023Inventors: Claudionor Jose Nunes Coelho, Jr., Piotr Zielinski, Aki Kuusela, Shan Li, Hao Zhuang
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Publication number: 20230123157Abstract: The present application discloses a method, system, and computer system for determining whether to train a machine learning model. The method includes analyzing a set of data for temporal drift detection, determining that a resultant stationary series has changed from training data, and in response to determining that the resultant stationary series has changed, automatically updating the machine learning model, wherein the machine learning model is trained based at least in part on a set of training data.Type: ApplicationFiled: January 21, 2022Publication date: April 20, 2023Inventors: Nandini Ramanan, Claudionor Jose Nunes Coelho Junior
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Publication number: 20230080654Abstract: Identifying causal relationships between outlier telemetry events in telemetry metric data using machine learning ensembles of an autoencoder and an attention mechanism provides an automated framework for root cause analysis. Outlier telemetry events are detected across a cloud of telemetry events using unsupervised learning models. To establish a causal relationship between outlier telemetry events, autoencoder/attention mechanism ensembles are trained for pairs of telemetry metrics. When inputs of sequences of telemetry events of a first telemetry metric and a second telemetry metric to the ensemble have sufficiently high loss value, a causal relationship is inferred. Internal node values of the attention mechanism from the input identify specific time stamps for the first telemetry metric that have a causal relationship with the outlier telemetry event.Type: ApplicationFiled: September 13, 2021Publication date: March 16, 2023Inventors: Zhen Han Si, Claudionor Jose Nunes Coelho, JR., Viswesh Ananthakrishnan, Eyal Firstenberg
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Publication number: 20220385635Abstract: A system generates vector representations of entries of traffic logs generated by a firewall. A first model learns contexts of values recorded in the logs during training, and the system extracts vector representations of the values from the trained model. For each log entry, vectors created for the corresponding values are combined to create a vector representing the entry. Cluster analysis of the vector representations can be performed to determine clusters of similar traffic and outliers indicative of potentially anomalous traffic. The system also generates a formal model representing firewall behavior which comprises formulas generated from the firewall rules. Proposed traffic scenarios not recorded in the logs can be evaluated based on the formulas to determine actions which the firewall would take in the scenarios. The combination of models which implement machine learning and formal techniques facilitates evaluation of both observed and hypothetical network traffic based on the firewall rules.Type: ApplicationFiled: September 13, 2021Publication date: December 1, 2022Inventors: Charanraj Thimmisetty, Praveen Tiwari, Viswesh Ananthakrishnan, Claudionor Jose Nunes Coelho, JR.
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Patent number: 9934410Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.Type: GrantFiled: September 19, 2016Date of Patent: April 3, 2018Assignee: Cadence Design Systems, Inc.Inventors: Victor Markus Purri, Caio Araújo Teixeira Campos, Magnus Björk, Lawrence Loh, Claudionor Jose Nunes Coelho
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Patent number: 9922209Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.Type: GrantFiled: September 19, 2016Date of Patent: March 20, 2018Assignee: Cadence Design Systems, Inc.Inventors: Victor Markus Purri, Caio Araújo Teixeira Campos, Magnus Björk, Lawrence Loh, Claudionor Jose Nunes Coelho
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Patent number: 9817930Abstract: Various mechanisms identify an electronic design model and determine a data propagation diagram by receiving a set of path property sources or destinations, determine a set of helper properties for the data propagation diagram by traversing at least a portion of the data propagation diagram, and verify the electronic design model by examining one or more helper properties and determining verification of the one or more helper properties leads to concrete results to generate verification results. Data propagation diagrams may be annotated with verification results to show verification progresses, highlight sources of complexity, and be further synchronized with waveform displays of one or more traces. Search space may be trimmed during a verification flow to enhance performance of verification engine(s). New start states closer to the final state than the default state may be identified during verification and used to enhance performance of the verification engine.Type: GrantFiled: December 31, 2014Date of Patent: November 14, 2017Assignee: Cadence Design Systems Inc.Inventors: Caio Araujo Texeira Campos, Tamires Vargas Campanema Franco Santos, Andrea Iabrudi Tavares, Fabiano Peixoto, Claudionor Jose Nunes Coelho, Jr.
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Patent number: 9659142Abstract: Disclosed are techniques for implementing trace warping for electronic designs. These techniques identify a portion of an electronic design including a set of signals of interest corresponding to a plurality of simulation combinations over a range of clock cycles in a trace display. A pair of matching simulation combinations is identified from one or more pairs of matching simulation combinations for the set of signals of interest; and a first clock cycle and a second clock cycle corresponding to the pair of matching simulation combinations are identified in the range of clock cycles. A plurality of clock cycles between the first clock cycle and the second clock cycle can be compressed in the trace display.Type: GrantFiled: October 6, 2015Date of Patent: May 23, 2017Assignee: Cadence Design Systems, Inc.Inventors: Claudionor Jose Nunes Coelho, Jr., Chung-Wah Norris Ip, Thiago Radicchi Roque
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Patent number: 9449196Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.Type: GrantFiled: April 22, 2013Date of Patent: September 20, 2016Assignee: Jasper Design Automation, Inc.Inventors: Victor Markus Purri, Caio Araújo Teixeira Campos, Magnus Björk, Lawrence Loh, Claudionor Jose Nunes Coelho
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Patent number: 9081927Abstract: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.Type: GrantFiled: October 4, 2013Date of Patent: July 14, 2015Assignee: JASPER DESIGN AUTOMATION, INC.Inventors: Claudionor José Nunes Coelho, Jr., Chien-Liang Lin, Chung-Wah Norris Ip
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Publication number: 20150100933Abstract: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.Type: ApplicationFiled: October 9, 2013Publication date: April 9, 2015Applicant: Jasper Design Automation, Inc.Inventors: Claudionor José Nunes Coelho, JR., Chien-Liang Lin, Chung-Wah Norris Ip
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Publication number: 20150100932Abstract: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.Type: ApplicationFiled: October 4, 2013Publication date: April 9, 2015Applicant: Jasper Design Automation, Inc.Inventors: Claudionor José Nunes Coelho, JR., Chien-Liang Lin, Chung-Wah Norris Ip
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Patent number: 8990745Abstract: A viewer shows circuit design activities, displaying a signal, its corresponding trace, and the values of the trace over time. A global zoom-in, zoom-out, and zoom-fit are provided over the value display to adjust the time interval covered within the viewer. Non-linear manipulation of the traces within the viewer enables simultaneous zoomed in display of multiple time intervals, and zoomed out display of other time intervals. The non-linear manipulations may be performed within a same display region by designating zoom groups corresponding to the selection of a designated time period of activities of the circuit. Each zoom group may be scaled independently of other timer periods to zoom in or out of activities occurring within the designated time period. A list of behaviors may also be provided. Selection of a behavior generates a separate signal list for signals associated with the behavior and corresponding traces for enhanced debugging.Type: GrantFiled: October 9, 2013Date of Patent: March 24, 2015Assignee: Jasper Design Automation, Inc.Inventors: Claudionor José Nunes Coelho, Chien-Liang Lin, Chung-Wah Norris Ip
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Patent number: 8572527Abstract: An analysis tool that generates properties for a circuit design. The debugging tool receives a circuit design encoded in a hardware description language. The tool identifies portions of the circuit design that correspond to features of interest (e.g., counters, finite state machines, one hot vectors, etc) in the circuit design. Each portion of the circuit design has a cone of influence, and the tool identifies control signals from within the cones of influence. By identifying control signals in this manner, the tool can then generate the properties based on values for the control signals and the identified portions of the circuit design that are obtained from data describing the operation of the circuit design over a number of clock cycles (e.g., simulation data). The result is one or more properties that are likely to represent a relevant behavior of the circuit design.Type: GrantFiled: September 13, 2011Date of Patent: October 29, 2013Assignee: Jasper Design Automation, Inc.Inventors: Claudionor José Nunes Coelho, Jr., Fabiano Cruz Peixoto
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Patent number: 8527911Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.Type: GrantFiled: June 9, 2010Date of Patent: September 3, 2013Assignee: Jasper Design Automation, Inc.Inventors: Kathryn Drews Kranen, Chung-Wah Norris Ip, Rajeev Kumar Ranjan, Georgia Penido Safe, Claudionor José Nunes Coelho, Yann Alain Antonioli
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Patent number: 8458621Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.Type: GrantFiled: June 9, 2010Date of Patent: June 4, 2013Assignee: Jasper Design Automation, Inc.Inventors: Kathryn Drews Kranen, Chung-Wah Norris Ip, Rajeev Kumar Ranjan, Georgia Penido Safe, Claudionor José Nunes Coelho, Yann Alain Antonioli
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Patent number: 8205187Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.Type: GrantFiled: June 9, 2010Date of Patent: June 19, 2012Assignee: Jasper Design Automation, Inc.Inventors: Claudionor José Nunes Coelho, Chung-Wah Norris Ip, Harry David Foster, Rajeev Kumar Ranjan, Kathryn Drews Kranen, Georgia Penido Safe