Abstract: For the integration of an npn bipolar transistor with a hetero bipolar transistor, a placeholder layer is generated in a base region of the hetero bipolar transistor after structuring a collector structure for both types of transistors, wherein the placeholder layer is not present in a base region of the bipolar transistor. After generating the base of the bipolar transistor, the base of the bipolar transistor is covered, whereupon the placeholder layer is removed and the base of the hetero bipolar transistor is generated in the places where the placeholder layer has been removed. The emitter structure is again generated equally for both types of transistors so that an integrated circuit results which includes bipolar transistors and hetero bipolar transistors whose collector structures and/or whose emitter structures consist of identical production layers. Thus, space-saving and cost-effective integrated circuits may be produced benefiting from the advantages of both types of transistors.

Abstract: Method for producing a planar spacer, an associated bipolar transistor and an associated BiCMOS circuit arrangement. The invention relates to a method for production of a planar spacer, of an associated bipolar transistor and of an associated BiCMOS circuit arrangement, in which first and second spacer layers are formed after the formation of a sacrificial mask on a mount substrate. A first anisotropic etching process of the second spacer layer is carried out to produce auxiliary spacers. A second anisotropic etching step is then carried out, in order to produce the planar spacers, using the auxiliary spacers as an etch mask.

Abstract: A method for producing a capacitor comprises providing a raw structure having a substrate and at least one dielectric layer, wherein a first area and a second area of the substrate are separated by an isolating layer. Above the first and second areas, an electrically conductive layer is arranged on the at least one dielectric layer. Further, a mask layer is deposited on the electrically conductive layer, wherein it is structured for generating a first mask above the first area. The method further comprises etching away the electrically conductive layer and at least one of the dielectric layers in the second area by means of the first mask and completing an active device in the second area.

Abstract: For the integration of an npn bipolar transistor with a hetero bipolar transistor, a placeholder layer is generated in a base region of the hetero bipolar transistor after structuring a collector structure for both types of transistors, wherein the placeholder layer is not present in a base region of the bipolar transistor. After generating the base of the bipolar transistor, the base of the bipolar transistor is covered, whereupon the placeholder layer is removed and the base of the hetero bipolar transistor is generated in the places where the placeholder layer has been removed. The emitter structure is again generated equally for both types of transistors so that an integrated circuit results which includes bipolar transistors and hetero bipolar transistors whose collector structures and/or whose emitter structures consist of identical production layers. Thus, space-saving and cost-effective integrated circuits may be produced benefiting from the advantages of both types of transistors.

Abstract: The invention concerns a water treatment method which consists in introducing coagulated water in a flocculation zone, to enable flocculation of microflocs in the presence and around a ballast; introducing the mixture in a decantation zone; separating the treated water in overflow and a mixture of sludge and the ballast in underflow; conveying at least part of said mixture to a sludge/ballast separating system and recycling into or upstream of the flocculation zone the ballast and part of the sludge introduced in said separation system.

Abstract: A method for producing a capacitor comprises providing a raw structure having a substrate and at least one dielectric layer, wherein a first area and a second area of the substrate are separated by an isolating layer. Above the first and second areas, an electrically conductive layer is arranged on the at least one dielectric layer. Further, a mask layer is deposited on the electrically conductive layer, wherein it is structured for generating a first mask above the first area. The method further comprises etching away the electrically conductive layer and at least one of the dielectric layers in the second area by means of the first mask and completing an active device in the second area.

Abstract: The three-transistor DRAM cell has a memory transistor formed as a field-effect transistor with a short-channel section and a long-channel section. A second insulating layer and a conductive layer are additionally formed on a gate layer of the memory transistor. A substantially constant voltage value is present between a potential of the conductive layer and a potential of the substrate area.

Abstract: The three-transistor DRAM cell has a memory transistor formed as a field-effect transistor with a short-channel section and a long-channel section. A second insulating layer and a conductive layer are additionally formed on a gate layer of the memory transistor. A substantially constant voltage value is present between a potential of the conductive layer and a potential of the substrate area.

Abstract: Integrated transistors and other semiconductor elements are formed on a substrate. Spacers are applied for the purpose of producing LDD regions. A layer of polysilicon is first deposited in full-surface coverage and then removed except for spacers remaining on gate structures. The layer of polysilicon is utilized for the purpose of producing further integrated components and, for this purpose, is covered by an auxiliary layer and the latter in turn by an auxiliary mask. During the etching of the polysilicon layer, the structures covered by the auxiliary mask are preserved and can be utilized for further integrated components. The etching which is necessary for removing the spacers is effected selectively such that remaining structures of the auxiliary layer and thus of the underlying layer of polysilicon are not attacked. The components produced in addition are preserved.