Abstract: To reduce the mean access time to storage blocks in CCD storage, a block which is most likely to be accessed next is detected after each access. While the accessed block is being processed, a selected block is moved at the high cyclic speed of the CCD storage to a shift position, and the CCD storage is then switched to the low speed. The distance of the shift position from a read/write position is such that it can be covered by the selected block at low speed within the mean time between two accesses to the CCD storage. At the time of the next access, the selected block is very likely to be close to the read/write position. In systems with virtual addressing, the block with the next virtual address would be the selected block. In other layouts, the access sequences to the CCD blocks are stored and are subsequently used to select the block which is most likely to be accessed next.

Abstract: Method and apparatus for controlling a stepping motor by storing in a memory, delay time values for the application of motor advance pulses and using motor feedback pulses to access the memory and read out corresponding time delay values after each of which a motor advance pulse is to be generated. The stored time delay values are optimized as to phase angle for the motor advance pulses for acceleration, constant run and deceleration modes of the motor after consideration of motor characteristics and load. Not all feedback pulses have a corresponding time delay value and certain feedback pulses may have two or more time delay values stored therefor. Also disclosed are improved motor coil switching circuits.

Abstract: For associative operation of a storage circuit, two field-effect transistors form one storage cell, i. e. that together with associated capacitors they store either a 1 or a 0. A word line is connected to one electrode of each field-effect transistor in a storage row. At one end of the word line a sensing amplifier with latch characteristics is arranged so that the information sensed by this circuit is amplified and subsequently latched or stored. For the associative operation of the circuit arrangement, two query lines Q0 and Q1 are provided for a bit position. When only one field-effect transistor with a series-connected capacitor is used, the bits of one bit position of the various words are simultaneously written, and the bit positions are addressed one after the other. For a bit position which is queried by means of a key or an identifier word bit "1" the true value of the bit is applied.