Abstract: An integrated circuit device is provided comprising a circuit board and one or more digital signal processors implemented thereon. The digital signal processor comprises a data unit comprising a function core configured to perform a specific mathematical expression in order to perform at least a portion of a specific application and an instruction memory storing one or more instructions configured to send commands to the control unit and the data unit to perform the specific application, and a control unit configured to control the flow of data between a plurality of memory banks and the function core for performing the specific application, and the plurality of memory banks coupled to each of the one or more digital signal processors and comprising at least two or more local memory banks integrated onto the circuit board.

Abstract: An integrated circuit device is provided comprising a circuit board and one or more digital signal processors implemented thereon. The digital signal processor comprises a data unit comprising a function core configured to perform a specific mathematical expression in order to perform at least a portion of a specific application and an instruction memory storing one or more instructions configured to send commands to the control unit and the data unit to perform the specific application, and a control unit configured to control the flow of data between a plurality of memory banks and the function core for performing the specific application, and the plurality of memory banks coupled to each of the one or more digital signal processors and comprising at least two or more local memory banks integrated onto the circuit board.

Abstract: A high precision weighted random pattern generation system generates any desired probability of individual bits within a weighted random bit pattern. The system includes a circular memory having a series of weighting factors stored therein, with each weighting factor representing the desired probability of a bit in the weighted random pattern being binary ONE. The random bits from a random number generator and a weighting factor are combined to form a single weighted random bit. The random bits and weighting factor are combined in a series of interconnected multiplexor gates. Each multiplexor gate has two data inputs, one being a bit from the weighting factor, the other being the output of the preceding multiplexor gate. The random number bit controls the output of the multiplexor. For example, when the control input (random bit) is high, the multiplexor output is the weighting factor bit. When the control input (random bit) is low, the multiplexor output is the output of the preceding multiplexor.