Patents by Inventor Clayton D. Andreasen

Clayton D. Andreasen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10698813
    Abstract: A system is provided for allocating memory for data of a program for execution by a computer system with a multi-tier memory that includes LBM and HBM. The system accesses a data structure map that maps data structures of the program to the memory addresses within an address space of the program to which the data structures are initially allocated. The system executes the program to collect statistics relating to memory requests and memory bandwidth utilization of the program. The system determines an extent to which each data structure is used by a high memory utilization portion of the program based on the data structure map and the collected statistics. The system generates a memory allocation plan that favors allocating data structures in HBM based on the extent to which the data structures are used by a high memory utilization portion of the program.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: June 30, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Heidi Lynn Poxon, William Homer, David W. Oehmke, Luiz DeRose, Clayton D. Andreasen, Sanyam Mehta
  • Patent number: 10185659
    Abstract: A system is provided for allocating memory for data of a program for execution by a computer system with a multi-tier memory that includes LBM and HBM. The system accesses a data structure map that maps data structures of the program to the memory addresses within an address space of the program to which the data structures are initially allocated. The system executes the program to collect statistics relating to memory requests and memory bandwidth utilization of the program. The system determines an extent to which each data structure is used by a high memory utilization portion of the program based on the data structure map and the collected statistics. The system generates a memory allocation plan that favors allocating data structures in HBM based on the extent to which the data structures are used by a high memory utilization portion of the program.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: January 22, 2019
    Assignee: Cray, Inc.
    Inventors: Heidi Lynn Poxon, William Homer, David W. Oehmke, Luiz DeRose, Clayton D. Andreasen, Sanyam Mehta
  • Publication number: 20180322064
    Abstract: A system is provided for allocating memory for data of a program for execution by a computer system with a multi-tier memory that includes LBM and HBM. The system accesses a data structure map that maps data structures of the program to the memory addresses within an address space of the program to which the data structures are initially allocated. The system executes the program to collect statistics relating to memory requests and memory bandwidth utilization of the program. The system determines an extent to which each data structure is used by a high memory utilization portion of the program based on the data structure map and the collected statistics. The system generates a memory allocation plan that favors allocating data structures in HBM based on the extent to which the data structures are used by a high memory utilization portion of the program.
    Type: Application
    Filed: July 12, 2018
    Publication date: November 8, 2018
    Inventors: Heidi Lynn Poxon, William Homer, David W. Oehmke, Luiz DeRose, Clayton D. Andreasen, Sanyam Mehta
  • Publication number: 20180165209
    Abstract: A system is provided for allocating memory for data of a program for execution by a computer system with a multi-tier memory that includes LBM and HBM. The system accesses a data structure map that maps data structures of the program to the memory addresses within an address space of the program to which the data structures are initially allocated. The system executes the program to collect statistics relating to memory requests and memory bandwidth utilization of the program. The system determines an extent to which each data structure is used by a high memory utilization portion of the program based on the data structure map and the collected statistics. The system generates a memory allocation plan that favors allocating data structures in HBM based on the extent to which the data structures are used by a high memory utilization portion of the program.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 14, 2018
    Inventors: Heidi Lynn Poxon, William Homer, David W. Oehmke, Luiz DeRose, Clayton D. Andreasen, Sanyam Mehta
  • Publication number: 20170206068
    Abstract: An optimization system to apply directives to a computer program without having to perform repeated front-end compilations of source code of the computer program is provided. In some embodiments, the optimization system performs a first compilation of the source code of the program to generate first front-end code and first back-end code of the computer program. The compilation includes a first front-end compilation and a first back-end compilation. The optimization system identifies a compiler directive to apply to a location within the first front-end code. The optimization system then performs a second back-end compilation of the first front-end code factoring in the compiler directive to generate second back-end code affected by the compiler directive.
    Type: Application
    Filed: May 9, 2016
    Publication date: July 20, 2017
    Inventors: Brian H. Johnson, Heidi Poxon, Luiz DeRose, Gary W. Elsesser, Clayton D. Andreasen, John Levesque
  • Patent number: 8332596
    Abstract: An error message handling buffer comprises a first buffer and a second buffer. A first index is associated with the first buffer and a second index is associated with the second buffer. A buffer controller is operable to write and read messages in the buffer, such that messages are written to the buffer of the first and second buffers that has a buffer index value lesser than the buffer size, and read from the other of the first and second buffers, the other buffer having an index value greater than or equal to the buffer size.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: December 11, 2012
    Assignee: Cray Inc.
    Inventor: Clayton D. Andreasen
  • Publication number: 20100318751
    Abstract: An error message handling buffer comprises a first buffer and a second buffer. A first index is associated with the first buffer and a second index is associated with the second buffer. A buffer controller is operable to write and read messages in the buffer, such that messages are written to the buffer of the first and second buffers that has a buffer index value lesser than the buffer size, and read from the other of the first and second buffers, the other buffer having an index value greater than or equal to the buffer size.
    Type: Application
    Filed: June 12, 2009
    Publication date: December 16, 2010
    Applicant: Cray Inc.
    Inventor: Clayton D. Andreasen
  • Patent number: 7401238
    Abstract: A distributed computing system contains one or more application nodes. One or more control nodes provide for the efficient and automated allocation and management of computing functions and resources within the distributed computing system. The control node includes an automation subsystem that provides autonomic power control for the application nodes, regardless of which vendor manufactured the application nodes. For power controllers not specifically supported by the distributed computing system, a universal power controller responds to power down instructions by causing a targeted application node to execute an idle software image and reports that the application node has been successfully powered down.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: July 15, 2008
    Assignee: Cassatt Corporation
    Inventors: Craig A. Lindley, Clayton D. Andreasen, Dann M. Church, James D. Engquist
  • Patent number: 5257372
    Abstract: Three new, efficient protocols for providing communications between a user's application program, a Multiprocessing Library, and the host Operating System is described. These new protocols are termed WAKEUP, GIVEUP, and CONTEXT-TO-USER-SPACE. They utilize the concept of a conduit through which the Operating System and the user application program can communicate without the need for expensive system calls. A primary use for the new protocols is the scheduling of multiple Central Processing Units (CPUs) into a single user program in a multi-CPU, multiprogramming, multi-tasking environment. WAKEUP allows a master process to quickly request the asynchronous scheduling of slave processes to help execute parallel tasks. GIVEUP allows a slave process time to finish a task before Operating System interruption. Once completed with its task, there is no need to save the context of the slave process.
    Type: Grant
    Filed: December 19, 1990
    Date of Patent: October 26, 1993
    Assignee: Cray Research, Inc.
    Inventors: Mark Furtney, Frank R. Barriuso, Clayton D. Andreasen, Timothy W. Hoel, Suzanne L. LaCroix, Steven P. Reinhardt