Abstract: A method of configuring an analog-to-digital converter (ADC) includes configuring the ADC to operate in one of a low-pass filter mode and a band-pass filter mode according to a value of a control signal. In at least one embodiment, the method further includes configuring an integrator gain of the ADC and a feed-forward gain of the ADC based on selection of one of a low-intermediate frequency (LIF) mode and a zero-intermediate frequency (ZIF) mode.

Abstract: A method of configuring an analog-to-digital converter (ADC) includes configuring the ADC to operate in one of a low-pass filter mode and a band-pass filter mode according to a value of a control signal. In at least one embodiment, the method further includes configuring an integrator gain of the ADC and a feed-forward gain of the ADC based on selection of one of a low-intermediate frequency (LIF) mode and a zero-intermediate frequency (ZIF) mode.

Abstract: A PGIA for use in measurement devices (e.g., data acquisition device) including a composite amplifier for level shifting and improved signal-to-noise ratio. The composite amplifier may level shift from a constant common mode voltage to a lower common mode voltage with a large voltage swing. The large output signal swing of the PGIA may allow excellent signal-to-noise ratio. Additionally, input op-amps of the PGIA may be bootstrapped so that their supply rails move according to an input signal of the PGIA. The PGIA may also include protection circuitry to protect components from damage, e.g., due to over-current conditions, and to keep all op-amps in proper closed loop operation. Furthermore, the PGIA may include DA compensation circuitry to cancel some dielectric absorptions effects and improve a step response of the PGIA and CMRR enhancement circuitry to increase symmetry at inputs of the PGIA and improve a CMRR associated with the PGIA.

Abstract: A calibration unit and technique for calibrating A/D systems (e.g., data acquisition devices) using a pulse-width modulation (PWM) circuit to reduce nonlinearity. The calibration unit may be coupled to an analog-to-digital module (ADM) of the A/D system. The PWM circuit may generate a calibration signal with intentional ripple, which may exercise a region of a transfer curve of the ADM to reduce local nonlinearities in measurements associated with the calibration of the system. Pulse trains of varying frequency and duty cycle may be generated to sweep the PWM circuit through an ADM range and to calculate an ADM linearity correction function, which may be used to perform gain and offset correction with respect to a best-fit line through an ADM transfer curve to reduce large signal nonlinearities. The PWM circuit may include a resistor divider circuit including a plurality of taps to calibrate small input ranges.

Abstract: A PGIA for use in measurement devices (e.g., data acquisition device) having improved dielectric absorption (DA) compensation and common mode rejection ratio (CMRR). When a step function is applied to an input of the PGIA, a first and a second DA compensation circuit may generate DA compensation signals derived from the step function. The DA compensation signals may combine with an original response of the PGIA to cancel some of the dielectric absorptions effects and improve the overall step response of the PGIA. An input stage of the PGIA may include a CMRR enhancement circuit to increase symmetry at the inputs of the PGIA. The CMRR enhancement circuit may delay an input signal received at a negative input terminal a particular amount such that it is in phase with an input signal received at a positive input terminal of the PGIA, to improve the CMRR.