Abstract: Disclosed is a digital computer memory system which coordinates between plural memories such that information recall from memories having different inherent access times results in a flow of only relevant data to the processor; this is accomplished in, for instance, a dual memory system, by synchronizing the operation of the memories such that the normal clock pulse of the computer strobes the output register of the faster (i.e., "normal") memory but a delayed clock pulse strobes the output register of the slower memory. Thus, because of the delayed strobe, the latter, as well as the former, has time to complete an access requested by the processor, and, consequently, transfer to the processor of incorrect or meaningless information is avoided.