Patents by Inventor Clemens Wündisch

Clemens Wündisch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9076818
    Abstract: A method for fabricating a semiconductor device includes forming first and second gate structures overlying the semiconductor substrate, and depositing a layer of a silicide-resistant material over the first and second gate structures and over the semiconductor substrate. The method further includes forming sidewall spacers from the layer of silicide-resistant material adjacent the first gate structure and removing the silicide-resistant material adjacent the sidewall spacers to expose the silicon substrate in a source and drain region. Still further, the method includes implanting conductivity determining impurities in the source and drain region, depositing a silicide forming metal, and annealing the semiconductor device to form a silicide in the source and drain region. The silicide-resistant material is not removed from over the second gate structure so as to prevent silicide formation at the second gate structure.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: July 7, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Andreas Kurz, Peter Javorka, Sergej Mutas, Clemens Wündisch
  • Publication number: 20130344673
    Abstract: A method for fabricating a semiconductor device includes forming first and second gate structures overlying the semiconductor substrate, and depositing a layer of a silicide-resistant material over the first and second gate structures and over the semiconductor substrate. The method further includes forming sidewall spacers from the layer of silicide-resistant material adjacent the first gate structure and removing the silicide-resistant material adjacent the sidewall spacers to expose the silicon substrate in a source and drain region. Still further, the method includes implanting conductivity determining impurities in the source and drain region, depositing a silicide forming metal, and annealing the semiconductor device to form a silicide in the source and drain region. The silicide-resistant material is not removed from over the second gate structure so as to prevent silicide formation at the second gate structure.
    Type: Application
    Filed: June 20, 2012
    Publication date: December 26, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Andreas Kurz, Peter Javorka, Sergej Mutas, Clemens Wündisch