Patents by Inventor Clement Charbuillet

Clement Charbuillet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transistor test structure
    Patent number: 9000785
    Abstract: A test structure may characterize the properties of a transistor including a DC test structure for testing DC properties of the transistor, and an AC test structure for testing AC properties of the transistor. The DC and AC test structures may have common test pads.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics SA
    Inventors: Clement Charbuillet, Patrick Scheer
  • Microelectromechanical device packaging with an anchored cap and its manufacture
    Patent number: 8871606
    Abstract: Integrated circuit (1) comprising a substrate (2), an active component (13) above the substrate (2), a cavity (14) surrounding partially the active component (13), a low dielectric region (15) surrounding partially the cavity (14) and a protective barrier (16) arranged around the low dielectric region (15).
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: October 28, 2014
    Assignees: STMicroelectronics (Crolles 2) SAS, Koninklijke Philips Electronics, N.V.
    Inventors: Clement Charbuillet, Laurent Gosset
  • TRANSISTOR TEST STRUCTURE
    Publication number: 20130027066
    Abstract: A test structure may characterize the properties of a transistor including a DC test structure for testing DC properties of the transistor, and an AC test structure for testing AC properties of the transistor. The DC and AC test structures may have common test pads.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 31, 2013
    Applicant: STMicroelectronics SA
    Inventors: Clement Charbuillet, Patrick Scheer
  • Microelectromechanical device packaging with an anchored cap and its manufacture
    Publication number: 20100001368
    Abstract: Integrated circuit (1) comprising a substrate (2), an active component (13) above the substrate (2), a cavity (14) surrounding partially the active component (13), a low dielectric region (15) surrounding partially the cavity (14) and a protective barrier (16) arranged around the low dielectric region (15).
    Type: Application
    Filed: August 24, 2006
    Publication date: January 7, 2010
    Inventors: Clement Charbuillet, Laurent Gosset
  • Vertical IMOS transistor having a PIN diode formed within
    Patent number: 7608867
    Abstract: A vertical IMOS-type transistor including: a stack of a first semiconductor portion doped with dopant elements of a first type, of a second substantially undoped intrinsic semiconductor portion, and of a third semiconductor portion doped with dopant elements of a second type forming a PIN-type diode; and a conductive gate placed against the stack with an interposed insulating layer.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: October 27, 2009
    Assignee: STMicroelectronics Crolles 2 SAS
    Inventors: Clément Charbuillet, Thomas Skotnicki, Alexandre Villaret
  • IMOS transistor
    Publication number: 20060220086
    Abstract: A vertical IMOS-type transistor including: a stack of a first semiconductor portion doped with dopant elements of a first type, of a second substantially undoped intrinsic semiconductor portion, and of a third semiconductor portion doped with dopant elements of a second type forming a PIN-type diode; and a conductive gate placed against the stack with an interposed insulating layer.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 5, 2006
    Applicant: STMicroelectronics Crolles 2 SAS
    Inventors: Clement Charbuillet, Thomas Skotnicki, Alexandre Villaret