Patents by Inventor Clement Hsingjen Wann

Clement Hsingjen Wann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10978451
    Abstract: An embodiment complimentary metal-oxide-semiconductor (CMOS) device and an embodiment method of forming the same are provided. The embodiment CMOS device includes an n-type metal-oxide-semiconductor (NMOS) having a titanium-containing layer interposed between a first metal contact and an NMOS source and a second metal contact and an NMOS drain and a p-type metal-oxide-semiconductor (PMOS) having a PMOS source and a PMOS drain, the PMOS source having a first titanium-containing region facing a third metal contact, the PMOS drain including a second titanium-containing region facing a fourth metal contact.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Clement Hsingjen Wann, Chih-Hsin Ko, Cheng-Hsien Wu, Ding-Kang Shih, Hau-Yu Lin
  • Publication number: 20210104619
    Abstract: A method for forming a semiconductor structure is provided. The method includes the following operations. A substrate is received. A fin structure is formed on the substrate, and a dielectric layer is formed over the fin structure. A sacrificial gate is formed over the substrate. A portion of the dielectric layer is exposed through the sacrificial gate. Recesses are formed in the fin structure at two sides of the sacrificial gate. A cleaning operation is performed with an HF-containing plasma. The HF-containing plasma includes HF and NH3.
    Type: Application
    Filed: November 23, 2020
    Publication date: April 8, 2021
    Inventors: CHUN HSIUNG TSAI, RU-SHANG HSIAO, CLEMENT HSINGJEN WANN
  • Patent number: 10971594
    Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Wen Liu, Clement Hsingjen Wann, Ming-Huan Tsai, Zhao-Cheng Chen
  • Patent number: 10943995
    Abstract: A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Wei-Chun Tsai
  • Patent number: 10916469
    Abstract: A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOI”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOI substrate is included.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: February 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, Limited
    Inventors: Yi-Tang Lin, Chun Hsiung Tsai, Clement Hsingjen Wann
  • Publication number: 20210036097
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.
    Type: Application
    Filed: January 9, 2020
    Publication date: February 4, 2021
    Inventors: Chun-Hsiung Tsai, Shahaji B. More, Yu-Ming Lin, Clement Hsingjen Wann
  • Publication number: 20210036131
    Abstract: The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.
    Type: Application
    Filed: October 5, 2020
    Publication date: February 4, 2021
    Inventors: You-Ru Lin, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Publication number: 20210028069
    Abstract: A method includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; performing an operation on the substrate; removing the barrier layer from the first trench to expose the dielectric layer subsequent to the operation; and depositing a work function layer over the dielectric layer in the first trench.
    Type: Application
    Filed: October 9, 2020
    Publication date: January 28, 2021
    Inventors: YI-JING LEE, YA-YUN CHENG, HAU-YU LIN, I-SHENG CHEN, CHIA-MING HSU, CHIH-HSIN KO, CLEMENT HSINGJEN WANN
  • Publication number: 20210020761
    Abstract: A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; depositing a first dielectric layer and a second dielectric layer over the substrate; forming a dummy gate electrode over the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; forming an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and performing a treatment by introducing a trap-repairing element into at least one of the gate spacer, the second dielectric layer, the surface and the LDD regions at a time before the forming of the source/drain regions or subsequent to the formation of the ILD layer.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 21, 2021
    Inventors: CHUN HSIUNG TSAI, KUO-FENG YU, YU-MING LIN, CLEMENT HSINGJEN WANN
  • Patent number: 10879235
    Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Tang Lin, Clement Hsingjen Wann, Neng-Kuo Chen
  • Patent number: 10879065
    Abstract: A method of forming an integrated circuit structure includes forming an insulation layer over at least a portion of a substrate; forming a plurality of semiconductor pillars over a top surface of the insulation layer. The plurality of semiconductor pillars is horizontally spaced apart by portions of the insulation layer. The plurality of semiconductor pillars is allocated in a periodic pattern. The method further includes epitaxially growing a III-V compound semiconductor film from top surfaces and sidewalls of the semiconductor pillars.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsin Ko, Cheng-Hsien Wu, Clement Hsingjen Wann
  • Patent number: 10854708
    Abstract: A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chewn-Pu Jou, Chih-Hsin Ko, Po-Wen Chiu, Chao-Ching Cheng, Chun-Chieh Lu, Chi-Feng Huang, Huan-Neng Chen, Fu-Lung Hsueh, Clement Hsingjen Wann
  • Patent number: 10847636
    Abstract: A method for forming a semiconductor structure is provided. The method includes the following operations. A substrate is received. The substrate includes a fin structure, a semiconductor layer over the fin structure, and a dielectric layer sandwiched between the fin structure and the semiconductor layer. The semiconductor layer is patterned to form a sacrificial gate layer over a portion of the fin structure. A first cleaning operation is performed with a HF solution. Spacers are formed over sidewalls of the sacrificial gate layer. Recesses are formed in the fin structure at two sides of the sacrificial gate layer. A second cleaning operation is performed with an HF-containing plasma.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun Hsiung Tsai, Ru-Shang Hsiao, Clement Hsingjen Wann
  • Publication number: 20200365621
    Abstract: A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the first channel material is different from the lattice constant of the bulk substrate to introduce strain to the first channel material. The method further comprises fabricating a first semiconductor device layer on the bulk substrate with the strained first channel material, fabricating a buffer layer comprising dielectric material with a blanket top surface above the first semiconductor layer, bonding to the blanket top surface a bottom surface of a second substrate comprising a buried oxide with a second channel material above the buried oxide, and fabricating a second semiconductor device layer on the second substrate.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Yi-Tang Lin, Chun-Hsiung Tsai, Clement Hsingjen Wann
  • Publication number: 20200343088
    Abstract: A method includes receiving a structure having a substrate, a conductive feature over the substrate, and a dielectric layer over the conductive feature. The method further includes forming a hole in the dielectric layer to expose the conductive feature; forming a first metal-containing layer on sidewalls of the hole; and forming a second metal-containing layer in the hole and surrounded by the first metal-containing layer. The first and the second metal-containing layers include different materials. The method further includes applying a first chemical to recess the dielectric layer, resulting in a top portion of the first and the second metal-containing layers protruding above the dielectric layer; and applying a second chemical having fluorine or chlorine to the top portion of the first metal-containing layer to convert the top portion of the first metal-containing layer into a metal fluoride or a metal chloride.
    Type: Application
    Filed: January 6, 2020
    Publication date: October 29, 2020
    Inventors: Ru-Shang Hsiao, Chun Hsiung Tsai, Clement Hsingjen Wann
  • Publication number: 20200343373
    Abstract: In a method of manufacturing a semiconductor device including a field effect transistor (FET), a sacrificial region is formed in a substrate, and a trench is formed in the substrate. A part of the sacrificial region is exposed in the trench. A space is formed by at least partially etching the sacrificial region, an isolation insulating layer is formed in the trench and the space, and a gate structure and a source/drain region are formed. An air spacer is formed in the space under the source/drain region.
    Type: Application
    Filed: April 23, 2020
    Publication date: October 29, 2020
    Inventors: Chun Hsiung TSAI, Clement Hsingjen WANN, Kuo-Feng YU, Yi-Tang LIN, Yu-Ming LIN
  • Publication number: 20200343127
    Abstract: In a method of manufacturing a semiconductor device including a field effect transistor (FET), a sacrificial region is formed in a substrate, and a trench is formed in the substrate. A part of the sacrificial region is exposed in the trench. A space is formed by at least partially etching the sacrificial region, an isolation insulating layer is formed in the trench and the space, and a gate structure and a source/drain region are formed. An air spacer is formed in the space under the source/drain region.
    Type: Application
    Filed: December 31, 2019
    Publication date: October 29, 2020
    Inventors: Clement Hsingjen WANN, Chun Hsiung TSAI, Shahaji B. MORE, Che-Chih HSU, Chinyu SU, Po-Han TSENG, Wen Han HUNG
  • Publication number: 20200343339
    Abstract: A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.
    Type: Application
    Filed: April 23, 2020
    Publication date: October 29, 2020
    Inventors: Chun Hsiung TSAI, Chih-Hsin KO, Clement Hsingjen WANN, Ya-Yun CHENG
  • Publication number: 20200328307
    Abstract: An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin.
    Type: Application
    Filed: June 26, 2020
    Publication date: October 15, 2020
    Inventors: Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 10804163
    Abstract: A method of forming a semiconductor structure includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; removing the barrier layer from the first trench to expose the dielectric layer; depositing a work function layer over the dielectric layer in the first trench; and depositing a conductive layer over the work function layer in the first trench.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Jing Lee, Ya-Yun Cheng, Hau-Yu Lin, I-Sheng Chen, Chia-Ming Hsu, Chih-Hsin Ko, Clement Hsingjen Wann