Patents by Inventor Clement Hsingjen Wann

Clement Hsingjen Wann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11508627
    Abstract: A method includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; performing an operation on the substrate; removing the barrier layer from the first trench to expose the dielectric layer subsequent to the operation; and depositing a work function layer over the dielectric layer in the first trench.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Jing Lee, Ya-Yun Cheng, Hau-Yu Lin, I-Sheng Chen, Chia-Ming Hsu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 11502186
    Abstract: The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: You-Ru Lin, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Publication number: 20220352030
    Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.
    Type: Application
    Filed: July 14, 2022
    Publication date: November 3, 2022
    Inventors: Chun Hsiung TSAI, Yu-Ming LIN, Kuo-Feng YU, Ming-Hsi YEH, Shahaji B. MORE, Chandrashekhar Prakash SAVANT, Chih-Hsin KO, Clement Hsingjen WANN
  • Publication number: 20220336629
    Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.
    Type: Application
    Filed: July 6, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung TSAI, Clement Hsingjen Wann, Kuo-Feng Yu, Ming-Hsi Yeh, Shahaji B. More, Yu-Ming Lin
  • Patent number: 11450661
    Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yu Hsu, Yi-Tang Lin, Clement Hsingjen Wann, Chih-Sheng Chang, Wei-Chun Tsai, Jyh-Cherng Sheu, Chi-Yuan Shih
  • Patent number: 11450571
    Abstract: Methods of manufacturing a semiconductor structure are provided. One of the methods includes: receiving a substrate including a first conductive region of a first transistor and a second conductive region of a second transistor, wherein the first transistor and the second transistor have different conductive types; performing an amorphization on the first conductive region and the second conductive region; performing an implantation over the first conductive region of the first transistor; forming a contact material layer over the first conductive region and the second conductive region; performing a thermal anneal on the first conductive region and the second conductive region; and performing a laser anneal on the first conductive region and the second conductive region.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun Hsiung Tsai, Cheng-Yi Peng, Ching-Hua Lee, Chung-Cheng Wu, Clement Hsingjen Wann
  • Patent number: 11437493
    Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: September 6, 2022
    Inventors: Chun Hsiung Tsai, Clement Hsingjen Wann, Kuo-Feng Yu, Ming-Hsi Yeh, Shahaji B. More, Yu-Ming Lin
  • Patent number: 11437517
    Abstract: An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Publication number: 20220262924
    Abstract: A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; depositing a first dielectric layer and a second dielectric layer over the substrate; performing a first treatment by introducing a trap-repairing element on the first and second dielectric layers; forming a dummy gate electrode over the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; and forming an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Inventors: CHUN HSIUNG TSAI, KUO-FENG YU, YU-MING LIN, CLEMENT HSINGJEN WANN
  • Patent number: 11404322
    Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Hsiung Tsai, Yu-Ming Lin, Kuo-Feng Yu, Ming-Hsi Yeh, Shahaji B. More, Chandrashekhar Prakash Savant, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 11393914
    Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: July 19, 2022
    Inventors: Chun Hsiung Tsai, Clement Hsingjen Wann, Kuo-Feng Yu, Ming-Hsi Yeh, Shahaji B. More, Yu-Ming Lin
  • Patent number: 11362000
    Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Publication number: 20220148977
    Abstract: A semiconductor structure includes a substrate, a conductive feature over the substrate, a dielectric layer over the conductive feature and the substrate, and a structure disposed over and electrically connected to the conductive feature. The structure is partially surrounded by the dielectric layer and includes a first metal-containing layer and a second metal-contain layer surrounded by the first metal-containing layer. The first and the second metal-containing layers include different materials. A lower portion of the first metal-containing layer includes a transition metal or a transition metal nitride and an upper portion of the first metal-containing layer includes a transition metal fluoride or a transition metal chloride.
    Type: Application
    Filed: January 24, 2022
    Publication date: May 12, 2022
    Inventors: Ru-Shang Hsiao, Chun Hsiung Tsai, Clement Hsingjen Wann
  • Patent number: 11329139
    Abstract: A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; depositing a first dielectric layer and a second dielectric layer over the substrate; forming a dummy gate electrode over the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; forming an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and performing a treatment by introducing a trap-repairing element into at least one of the gate spacer, the second dielectric layer, the surface and the LDD regions at a time before the forming of the source/drain regions or subsequent to the formation of the ILD layer.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun Hsiung Tsai, Kuo-Feng Yu, Yu-Ming Lin, Clement Hsingjen Wann
  • Publication number: 20220102482
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.
    Type: Application
    Filed: December 13, 2021
    Publication date: March 31, 2022
    Inventors: Chun-Hsiung Tsai, Shahaji B. More, Yu-Ming Lin, Clement Hsingjen Wann
  • Publication number: 20220045190
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first barrier layer is formed on the gate dielectric layer, a second barrier layer is formed on the first barrier layer, a first work function adjustment layer is formed on the second barrier layer, the first work function adjustment layer and the second barrier layer are removed. After the first work function adjustment layer and the second barrier layer are removed, a second work function adjustment layer is formed over the gate dielectric layer, and a metal gate electrode layer is formed over the second work function adjustment layer.
    Type: Application
    Filed: October 25, 2021
    Publication date: February 10, 2022
    Inventors: Yi-Jing LEE, Chih-Hsin KO, Clement Hsingjen WANN
  • Patent number: 11233140
    Abstract: In a method of manufacturing a semiconductor device including a field effect transistor (FET), a sacrificial region is formed in a substrate, and a trench is formed in the substrate. A part of the sacrificial region is exposed in the trench. A space is formed by at least partially etching the sacrificial region, an isolation insulating layer is formed in the trench and the space, and a gate structure and a source/drain region are formed. An air spacer is formed in the space under the source/drain region.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: January 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hsiung Tsai, Clement Hsingjen Wann, Kuo-Feng Yu, Yi-Tang Lin, Yu-Ming Lin
  • Patent number: 11232943
    Abstract: A method includes receiving a structure having a substrate, a conductive feature over the substrate, and a dielectric layer over the conductive feature. The method further includes forming a hole in the dielectric layer to expose the conductive feature; forming a first metal-containing layer on sidewalls of the hole; and forming a second metal-containing layer in the hole and surrounded by the first metal-containing layer. The first and the second metal-containing layers include different materials. The method further includes applying a first chemical to recess the dielectric layer, resulting in a top portion of the first and the second metal-containing layers protruding above the dielectric layer; and applying a second chemical having fluorine or chlorine to the top portion of the first metal-containing layer to convert the top portion of the first metal-containing layer into a metal fluoride or a metal chloride.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: January 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Shang Hsiao, Chun Hsiung Tsai, Clement Hsingjen Wann
  • Patent number: 11201205
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsiung Tsai, Shahaji B. More, Yu-Ming Lin, Clement Hsingjen Wann
  • Publication number: 20210375694
    Abstract: Methods of manufacturing a semiconductor structure are provided. One of the methods includes the following operations. A substrate is received, and the substrate includes a first conductive region and a second conductive region. A first laser anneal is performed on the first conductive region to repair lattice damage. An amorphization is performed on the first conductive region and the second conductive region to enhance silicide formation to a desired phase transformation in the subsequent operations. A pre-silicide layer is formed on the substrate. A thermal anneal is performed to the substrate to form a silicide layer from the pre-silicide layer. A second laser anneal is performed on the first conductive region and the second conductive region.
    Type: Application
    Filed: August 9, 2021
    Publication date: December 2, 2021
    Inventors: CHUN HSIUNG TSAI, CHENG-YI PENG, CHING-HUA LEE, CLEMENT HSINGJEN WANN, YU-MING LIN