Patents by Inventor Clement Luk

Clement Luk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Mitigation of connector stub resonance
    Patent number: 10249989
    Abstract: Example implementations described herein are directed to a method and apparatus for improving insertion loss of connector stub and thereby increasing a system's signal bandwidth. This technique shapes the connector stub in a specific way to shift its resonant frequency higher while having equal or better electrical performance below the original resonant frequency.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: April 2, 2019
    Assignee: HIROSE ELECTRIC CO., LTD.
    Inventors: Clement Luk, Jeremy Buan, Tadashi Ohshida, Ching-Chao Huang
  • MITIGATION OF CONNECTOR STUB RESONANCE
    Publication number: 20180261961
    Abstract: Example implementations described herein are directed to a method and apparatus for improving insertion loss of connector stub and thereby increasing a system's signal bandwidth. This technique shapes the connector stub in a specific way to shift its resonant frequency higher while having equal or better electrical performance below the original resonant frequency.
    Type: Application
    Filed: January 24, 2018
    Publication date: September 13, 2018
    Inventors: Clement LUK, Jeremy BUAN, Tadashi OHSHIDA, Ching-Chao HUANG
  • Fringe RLGC model for interconnect parasitic extraction
    Publication number: 20050240883
    Abstract: An RLGC library is generated so as to include fringe RLCG functions for 2-D canonical interconnect structures. During parameter extraction for selected interconnect structures of an integrated circuit, printed circuit board, or integrated circuit package design, the RLGC library is used to generate fringe RLGC coefficients which in addition to area RLGC coefficients calculated on-the-fly, are used to generate equivalent RLGC circuits or S-parameters for simulating the interconnect structures.
    Type: Application
    Filed: April 22, 2004
    Publication date: October 27, 2005
    Inventors: Ching-Chao Huang, Clement Luk