Abstract: A CMOS timing device having a primary oscillatory reference source, a chain of series connected bistable divider stages whose data outputs are applied to a decoder/display by way of a multiplexing network. The multiplexing network is comprised of a plurality of multiplex sections, each section having a plurality of data transmission channels or paths. Each channel includes a plurality of MOS devices of a first type connected to a common bus. All channels driving the common bus share a single MOS device of a second type which provides a complementary function with respect to the first type to establish predetermined operating voltage levels for the data logic states carried by the common bus. The data on the common bus of each multiplex section is stored in a CMOS bistable latching type flip-flop whose regenerative feedback path is MOS device controlled.