Abstract: A method and system aggregate data on multiple physically separate lower-speed E1/J1 channels of a communications network to generate higher bandwidth. A high speed data stream is first divided into lower bandwidth channels and transmitted through the network. The data arrives with varying delays depending on the physical characteristics of the network. Low bandwidth channels are aggregated together into a high bandwidth channel by determining the different geographical delay parameters among the lower speed channels, adjusting the transmission delays by alignment circuitry, and then combining the lower speed signals into one high bandwidth channel for the user. The transmission delay adjustment consists in adding a pseudo-random noise pattern to each of the lower bandwidth channels, measuring the time difference among all the channels, and then adjusting the time differences in the received data stream so that the combination of the signals produces a coherent higher bandwidth data stream.

Abstract: A multipurpose data communication network node for interconnecting both ATM and Variable Length (VL) input/output trunks with all combinations of node input versus output trunk connections. The network node includes ATM/VL Receive Adapters and ATM/VL Transmit Adapters, interconnected via a Switching device (44) operating on ATM like packets (i.e. ATM cells) only. The receive adapter includes means (41, 43) for deriving switchable cells from VL traffic possibly including ATM packets and provided over an input VL trunk and means (45, 46) for deriving switchable cells from ATM packets provided on input ATM trunk. The transmit adapter, includes means (47, 48) for reconstructing VL traffic to be fed onto an output VL trunk, and means (49, 50) for reconstructing ATM traffic to be fed onto an output ATM trunk; both means (47, 48) and (49, 50) being fed with switchable cells irrespective of the traffic origin, being it from VL or ATM trunks.

Abstract: An elastic buffer is provided between two busses working with independent clocking. The buffer is implemented by a piece of RAM memory (37) partitioned into sectors (41), each of which contains successive memory addresses. Each sector (41), can be alternatively written and read, so that at a given moment, a sector in write mode and a sector in read mode may coexist. Each sector is controlled by a mark flag (MF), a set flag corresponding to a fully written sector, and a reset flag corresponding to a sector that has been read onto the destination bus. The mark flag of each sector is set, respectively reset, upon the event of a move in pointer, respectively move out pointer, reaching the next adjacent sector. For a given elastic buffer size, the size of the sectors (41) and the number of mark flags are adaptable to the specifications of the data flow between the origin and destination busses.

Abstract: Processing system for interpreting and carrying out a set of logically related instructions stored into a software program, the execution of a given instruction by the processing system involving the decoding and the execution of a corresponding set of microcommands. The processing system stores a signature portion corresponding to the macrocommand portion of a given instruction which is to be interpreted and executed, and signature data in response to the actual decoding and execution process of the microcommands involved in the execution of the instruction. The processing system further compares the computed signature data with the signature portion in order to detect the occurrence of an error in the decoding and execution process of the given instruction. In one embodiment of the invention, the processing system is such that one instruction is interpreted and executed in one elementary machine cycle.