Patents by Inventor Clement Tse

Clement Tse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10867333
    Abstract: Systems and methods for using logic design processing to create an integrated circuit (IC).
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: December 15, 2020
    Assignee: ARM Finance Overseas Limited
    Inventors: Soumya Banerjee, Todd Michael Bezenek, Clement Tse
  • Publication number: 20190392500
    Abstract: Systems and methods for using logic design processing to create an integrated circuit (IC).
    Type: Application
    Filed: August 12, 2019
    Publication date: December 26, 2019
    Inventors: Soumya Banerjee, Todd Michael Bezenek, Clement Tse
  • Patent number: 10097523
    Abstract: In order to provide secure user access to a device or service on a remote network, upon receipt of a request to access the device or service on a portal on a central server, a request is sent to a probe application installed on the remote network to establish a secure link to the central server. A message is then sent to the user directing the user to initiate a specific session request to the central server. The session request is cross connected to the probe application installed on the remote network over the secure link to establish a secure tunnel to the probe application. A secure user session is set up through the secure tunnel to the device or service via the probe application.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: October 9, 2018
    Assignee: Martello Technologies Corporation
    Inventors: Bill Kuker, Ryan Tenney, Clement Tse
  • Publication number: 20150154677
    Abstract: A software system for facilitating the design process and minimizing the time and effort required to complete the design and fabrication of an integrated circuits (IC) is described. The software system utilizes a data center having a plurality of repositories, rules engines and design and verification tools to automatically produce a hardened GDSII description or other representation of the device in response to the formation of a electronic license agreement. Designers select contractual terms for incorporating third party intellectual property and then design and initiate manufacture of the IC by way of a network portal.
    Type: Application
    Filed: February 9, 2015
    Publication date: June 4, 2015
    Inventors: Soumya Banerjee, Todd Michael Bezenek, Clement Tse
  • Publication number: 20150150114
    Abstract: In order to provide secure user access to a device or service on a remote network, upon receipt of a request to access the device or service on a portal on a central server, a request is sent to a probe application installed on the remote network to establish a secure link to the central server. A message is then sent to the user directing the user to initiate a specific session request to the central server. The session request is cross connected to the probe application installed on the remote network over the secure link to establish a secure tunnel to the probe application. A secure user session is set up through the secure tunnel to the device or service via the probe application.
    Type: Application
    Filed: January 30, 2012
    Publication date: May 28, 2015
    Applicant: MARTELLO TECHNOLOGIES CORPORATION
    Inventors: Bill Kuker, Ryan Tenney, Clement Tse
  • Patent number: 8103987
    Abstract: A system and methods that facilitate the design process and minimize the time and effort required to complete the design and fabrication of an integrated circuits (IC) are described. The system and method utilize a plurality of repositories, rules engines and design and verification tools to analyze the workload and automatically produce a hardened GDSII description or other representation of the device. The system and method securely maintains synthesizable RTL on a server in a data center while providing designers access to portions of the mechanism by way of a network portal.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: January 24, 2012
    Assignee: MIPS Technologies, Inc.
    Inventors: Soumya Banerjee, Todd Michael Bezenek, Clement Tse
  • Publication number: 20080222580
    Abstract: A system and methods that facilitate the design process and minimize the time and effort required to complete the design and fabrication of an integrated circuits (IC) are described. The system and method utilize a plurality of repositories, rules engines and design and verification tools to analyze the workload and automatically produce a hardened GDSII description or other representation of the device. The system and method securely maintains synthesizable RTL on a server in a data center while providing designers access to portions of the mechanism by way of a network portal.
    Type: Application
    Filed: March 9, 2007
    Publication date: September 11, 2008
    Applicant: MIPS TECHNOLOGIES, INC.
    Inventors: Soumya Banerjee, Todd Michael Bezenek, Clement Tse
  • Publication number: 20080222581
    Abstract: A software system for facilitating the design process and minimizing the time and effort required to complete the design and fabrication of an integrated circuits (IC) is described. The software system utilizes a data center having a plurality of repositories, rules engines and design and verification tools to automatically produce a hardened GDSII description or other representation of the device in response to the formation of a electronic license agreement. Designers select contractual terms for incorporating third party intellectual property and then design and initiate manufacture of the IC by way of a network portal.
    Type: Application
    Filed: March 9, 2007
    Publication date: September 11, 2008
    Applicant: MIPS TECHNOLOGIES, INC.
    Inventors: Soumya Banerjee, Todd Michael Bezenek, Clement Tse
  • Patent number: 7006155
    Abstract: A system for forming composite video images from one or more foreground images and one or more background images. In one embodiment, s sum of a suppressed foreground image signal with weight ?, with one or more selected foreground colors suppressed, and a background image signal with weight 1??? (0????1) is formed, where a and ?? may vary from pixel to pixel and with time. In another embodiment, a shadow from a selected foreground image is impressed on selected pixels of a background image. In another embodiment, foreground suppression and shadowing are combined, optionally by retrofitting, using an existing ?-mixer or a newly constructed ?-mixer. Provision of a chroma key map allows a foreground image shadow to be prescribed pixel by pixel, including a transition region in which the shadowed image slowly disappears.
    Type: Grant
    Filed: February 1, 2000
    Date of Patent: February 28, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vinay Agarwala, Clement Tse