Abstract: A low pass filter having a first mode of operation and a second mode of operation. The low pass filter includes a charging circuit, a capacitor circuit, and low power circuitry coupled to the capacitor circuit and the charging circuit. The capacitor circuit stores a first differential voltage when the low pass filter is operating in the first mode of operation. The capacitor circuit stores a second differential voltage when the low pass filter is operating in the second mode of operation. The second differential voltage is substantially equal to the first differential voltage. The charging circuit may include a charging current source coupled to a current steering circuit. The low pass filter may further include a load circuit coupled to the current steering circuit and the low power circuitry. The low pass filter may be used in a delay locked loop circuit or a phase locked loop circuit.

Abstract: A phase interpolater circuit includes a first adjustable current supply to generate a first current that is based on the amplitude of a first controlled voltage and a first current mirror circuit to generate a second current that is based on the first current. The phase interpolater circuit further includes a first current steering switch to steer the second current to one of first and second nodes to generate a first voltage transition at one of the first and second nodes, the second current being steered to the first node when a first input signal is in a first state and to the second node when the first input signal is in a second state.

Abstract: A duty cycle correcting amplifier includes a first differential transistor pair with a pair of input nodes for receiving a differential input signal to be amplified. The first differential transistor pair has a first common node and a first pair of output nodes carrying differential output signals. A first current source is connected between the first common node and a first supply voltage. A second differential transistor pair has a pair of input nodes for receiving differential error input signals. The second differential transistor pair has a second common node and a second pair of output nodes coupled to the first pair of output nodes. The second differential transistor pair alters the common mode levels of each of the first pair of output nodes based on the differential error input signals to affect the duty cycle of the differential output signals. A second current source is connected between the second common node and the first supply voltage.

Abstract: A phase interpolator with noise immunity. The phase interpolator includes a voltage-to-current conversion circuit that receives a differential voltage and generates a differential current. The differential current is mirrored and provided to a phase Max/Min detector circuit and current switches. The phase Max/Min detectors may generate signals for a phase selector circuit. The current switches provide the mirrored current to a phase comparator and a load circuit in response to input vectors and a quadrant select signal. The phase comparator generates output waveforms from the phase interpolator.

Abstract: A pulse generating circuit that includes an unbalanced latch and a feedback circuit. The unbalanced latch is configured to generate a latch signal having a predetermined state in response to application of power to the circuit. The feedback circuit is coupled in a negative feedback arrangement with the unbalanced latch and generates a pulse signal for a predetermined period of time in response to the latch signal.

Abstract: Circuitry for adjusting the phase of an incoming periodic signal, typically a clock signal, throughout the entire period of the periodic signal. Phase adjustment circuitry has high resolution and employs only the number of delay elements in a delay chain necessary to span at least the period of the incoming signal or at least half the period in the case of dual chains receiving complementary clocks. Phase adjustment circuitry includes a delay chain of having a plurality of taps, a boundary detector for indicating when a tap is at a phase boundary of the incoming periodic signal, and selection circuitry for selecting one of the taps from the delay chain based on the boundary detector output and the selection circuitry input such that the selected tap is the desired phase adjustment of the incoming periodic signal and that the delay of the incoming signal is adjustable across its phase boundaries.

Abstract: A method for creating a physical layout of an analog integrated circuit characterized by the steps of developing a library of device modules and then assembling the device modules in an iterative fashion to create the desired analog circuit. The iterative process is preferably performed in a computerized spreadsheet program by developing an initial tiling script for the device modules, calculating the operating specifications of the circuit produced by the tiling script, comparing the calculated operating specifications against the desired operating parameters of the circuit and modifying the tiling script and repeating the process until the calculated operating specifications meet the desired operating parameters. In one embodiment the desired operating parameters include operating parameters of the analog circuit taken as a whole and in another embodiment the desired operating parameters include operating parameters of individual devices within the analog circuit.