Abstract: Techniques are provided to control hotswap operations with programmable logic devices (PLDs). In particular, a MOSFET is provided to limit an in-rush current drawn from a power supply by capacitive components of an electronic assembly when it is plugged into the live, power supply. A controller with an algorithm is provided to control the MOSFET based on the in-rush current detected at the MOSFET. As such, a feedback control loop is established to selectively bias the gate of the MOSFET based on the detected in-rush current. The algorithm may limit the in-rush current based on a Safe Operating Area (SOA) of the MOSFET. The hotswap process may include multiple phases each with a voltage and/or current limit modeling the voltages and currents of the SOA. The algorithm may transition through the phases with the respective current and/or voltage limits during the hotswap process.

Abstract: In one embodiment, a system has a master programmable device (PD) with native dual-boot capability and one or more slave PDs with no native dual-boot capability. A master golden image includes an embedded dual-boot function. During power-up, each PD copies its primary image into its volatile configuration memory and determines whether the primary image is valid. When the master's configuration engine detects an invalid master primary image, then the master's native dual-boot capability enables the master to implement a system-reboot procedure, which includes copying the master golden image from an external memory device into the master's volatile configuration memory and launching the embedded dual-boot function, which in turn copies the slave golden images from the external memory device into the slaves' volatile configuration memories before enabling other master-golden-image functions. Significant system reliability and robustness are achieved without provisioning every PD with native dual-boot capability.

Abstract: Techniques are provided to control hotswap operations with programmable logic devices (PLDs). In particular, a MOSFET is provided to limit an in-rush current drawn from a power supply by capacitive components of an electronic assembly when it is plugged into the live, power supply. A controller with an algorithm is provided to control the MOSFET based on the in-rush current detected at the MOSFET. As such, a feedback control loop is established to selectively bias the gate of the MOSFET based on the detected in-rush current. The algorithm may limit the in-rush current based on a Safe Operating Area (SOA) of the MOSFET. The hotswap process may include multiple phases each with a voltage and/or current limit modeling the voltages and currents of the SOA. The algorithm may transition through the phases with the respective current and/or voltage limits during the hotswap process.

Abstract: In one embodiment, an electronic system includes a shared resource and multiple controllers connected to the shared resource by different resource interfaces. In order to coordinate control of the shared resource, which can be controlled by only one controller at a time, the system has an arbitration device that communicates with the multiple controllers over one or more arbitration interfaces (different from the resource interfaces). The arbitration device has a register that stores (i) a controller identification value that identifies one of the controllers and (ii) a control status value that indicates whether the identified controller currently controls the shared resource. Each controller reads data stored in the register to determine whether the shared resource is currently controlled by a controller, and each controller writes data to the first register to secure control of the shared resource, when the shared resource is not currently controlled by a controller.

Abstract: In one embodiment, a system has a master programmable device (PD) with native dual-boot capability and one or more slave PDs with no native dual-boot capability. A master golden image includes an embedded dual-boot function. During power-up, each PD copies its primary image into its volatile configuration memory and determines whether the primary image is valid. When the master's configuration engine detects an invalid master primary image, then the master's native dual-boot capability enables the master to implement a system-reboot procedure, which includes copying the master golden image from an external memory device into the master's volatile configuration memory and launching the embedded dual-boot function, which in turn copies the slave golden images from the external memory device into the slaves' volatile configuration memories before enabling other master-golden-image functions. Significant system reliability and robustness are achieved without provisioning every PD with native dual-boot capability.