Patents by Inventor Cliff Zitlaw
Cliff Zitlaw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11449441Abstract: A memory device that includes a first port and a second port. The first port includes a first clock input, at least one first command address input, and at least one data input or output configured to transfer data in relation to the memory device. The second port includes a second clock input and at least one command, address, and data input/output (I/O) configured to receive command and address information from, and to transfer data in relation to the memory device. The memory device also includes a plurality of memory banks, in which two different memory banks may be accessed respectively by the first and the second ports concurrently. Other embodiments of the memory device and related methods and systems are also disclosed.Type: GrantFiled: May 21, 2021Date of Patent: September 20, 2022Assignee: Cypress Semiconductor CorporationInventors: Yoram Betser, Cliff Zitlaw, Stephan Rosner, Kobi Danon, Amir Rochman
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Patent number: 11403172Abstract: A method can include, in response to receiving a read request at a memory controller, sending a read command and address values on a command address bus in synchronism with a clock. In response to the read command, receiving an uninterrupted burst of read data values on at least one parallel data bus, the burst of read data values having double date rate with respect to the clock, and receiving error correction code (ECC) values for the read data values in response to the same read command, the ECC values not being included in the burst of read data values being output on non-ECC input/outputs (I/Os); wherein the non-ECC I/Os are I/Os not assigned to ECC data according to a preexisting standards organization. Corresponding systems and devices are disclosed.Type: GrantFiled: March 23, 2020Date of Patent: August 2, 2022Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Morgan Andrew Whately, Cliff Zitlaw
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Patent number: 11385829Abstract: A device can include a plurality of processing sources; a multiplexer (MUX) configured to assign read requests from the processing sources to predetermined time division multiplexer (TDM) command slots. A memory controller can generate nonvolatile memory (NVM) command and address data from read requests received from the MUX during the TDM command slots assigned to the read requests on a unidirectional command-address bus. The address data can include at least a bank address. The device can also receive read data on a unidirectional parallel data bus in synchronism with rising and falling edges of a received data clock. The read data can be received in TDM read slots having a predetermined order. A demultiplexer can provide the read data of each TDM read slot to one of the processing sources based on the TDM read slot position in the predetermined order. Related methods and systems are also disclosed.Type: GrantFiled: December 18, 2019Date of Patent: July 12, 2022Assignee: Cypress Semiconductor CorporationInventors: Hans Van Antwerpen, Morgan Andrew Whately, Cliff Zitlaw
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Patent number: 11258772Abstract: An apparatus includes a non-volatile memory (NVM) device coupled to a host, the NVM device including a processing device to: receive a communication packet from a server via the host computing system that is coupled to the NVM device and communicatively coupled to the server, the communication packet comprising clear text data that requests to initiate secure communications; perform a secure handshake with the server, via communication through the host computing system, using a secure protocol that generates a session key; receive data, via the host computing system, from the server within a secure protocol packet, wherein the data is inaccessible to the host computing system; authenticate the data using secure protocol metadata of the secure protocol packet; optionally decrypt, using the session key, the data to generate plaintext data; and store the plaintext data in NVM storage elements of the NVM device.Type: GrantFiled: June 4, 2019Date of Patent: February 22, 2022Assignee: Cypress Semiconductor CorporationInventors: Sergey Ostrikov, Stephan Rosner, Cliff Zitlaw
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Patent number: 11210238Abstract: An apparatus including non-volatile memory to store a forensic key and data, the data received from a host computing system. A processing device is coupled to the non-volatile memory and is to: allow writing the data, by the host computing system, to a region of the non-volatile memory; in response to a lock signal received from the host computing system, assert a lock on the region of the non-volatile memory, the lock to cause a restriction on access to the region of the non-volatile memory by an external device; and provide unrestricted access, by the external device, to the region of the non-volatile memory in response to verification of the forensic key received from the external device.Type: GrantFiled: March 19, 2019Date of Patent: December 28, 2021Assignee: Cypress Semiconductor CorporationInventors: Avi Avanindra, Stephan Rosner, Cliff Zitlaw
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Publication number: 20210349839Abstract: A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.Type: ApplicationFiled: May 21, 2021Publication date: November 11, 2021Applicant: Cypress Semiconductor CorporationInventors: Yoram Betser, Cliff Zitlaw, Stephan Rosner, Kobi Danon, Amir Rochman
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Patent number: 11061663Abstract: Example apparatus, systems and methods receive a new firmware image at a memory device and place the new firmware image into second nonvolatile storage locations of the memory device such that the second nonvolatile storage locations do not overlap with first nonvolatile storage locations of the memory device that store a current firmware image. Embodiments place a logical address to physical address mapping for the new firmware image into a remap data structure stored in memory circuits of the memory device. The remap data structure also includes a logical address to physical address mapping for the current firmware image. Embodiments provide a first status value to indicate that the logical address to physical address mapping for the new firmware image is a valid firmware image and a second status value to indicate that the logical address to physical address mapping for the current firmware image is an invalid firmware image.Type: GrantFiled: January 6, 2020Date of Patent: July 13, 2021Assignee: Cypress Semiconductor CorporationInventors: Stephan Rosner, Sergey Ostrikov, Cliff Zitlaw, Yuichi Ise
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Patent number: 11030128Abstract: A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.Type: GrantFiled: December 18, 2019Date of Patent: June 8, 2021Assignee: Cypress Semiconductor CorporationInventors: Yoram Betser, Cliff Zitlaw, Stephan Rosner, Kobi Danon, Amir Rochman
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Publication number: 20210042245Abstract: A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.Type: ApplicationFiled: December 18, 2019Publication date: February 11, 2021Applicant: Cypress Semiconductor CorporationInventors: Yoram Betser, Cliff Zitlaw, Stephan Rosner, Kobi Danon, Amir Rochman
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Publication number: 20210042054Abstract: A device can include a plurality of processing sources; a multiplexer (MUX) configured to assign read requests from the processing sources to predetermined time division multiplexer (TDM) command slots. A memory controller can generate nonvolatile memory (NVM) command and address data from read requests received from the MUX during the TDM command slots assigned to the read requests on a unidirectional command-address bus. The address data can include at least a bank address. The device can also receive read data on a unidirectional parallel data bus in synchronism with rising and falling edges of a received data clock. The read data can be received in TDM read slots having a predetermined order. A demultiplexer can provide the read data of each TDM read slot to one of the processing sources based on the TDM read slot position in the predetermined order. Related methods and systems are also disclosed.Type: ApplicationFiled: December 18, 2019Publication date: February 11, 2021Applicant: Cypress Semiconductor CorporationInventors: Hans Van Antwerpen, Morgan Andrew Whately, Cliff Zitlaw
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Publication number: 20210042189Abstract: A method can include, in response to receiving a read request at a memory controller, sending a read command and address values on a command address bus in synchronism with a clock. In response to the read command, receiving an uninterrupted burst of read data values on at least one parallel data bus, the burst of read data values having double date rate with respect to the clock, and receiving error correction code (ECC) values for the read data values in response to the same read command, the ECC values not being included in the burst of read data values being output on non-ECC input/outputs (I/Os); wherein the non-ECC I/Os are I/Os not assigned to ECC data according to a preexisting standards organization. Corresponding systems and devices are disclosed.Type: ApplicationFiled: March 23, 2020Publication date: February 11, 2021Applicant: Cypress Semiconductor CorporationInventors: Morgan Andrew Whately, Cliff Zitlaw
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Patent number: 10868679Abstract: A device can include a plurality of regions, each region including a plurality of nonvolatile memory cells: a permission store configured to store a set of permission values, including at least one permission value for each region in a nonvolatile fashion; and access control circuits configured to control access to each region according to the permission value for the region, including one or more of requiring authentication to access the region, encrypting data read from the region, and decrypting data for storage in the region. Related methods and systems are also disclosed.Type: GrantFiled: March 23, 2020Date of Patent: December 15, 2020Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Hans Van Antwerpen, Cliff Zitlaw, Stephan Rosner, Yoav Yogev, Sandeep Krishnegowda, Steven Wilson
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Publication number: 20200301698Abstract: Example apparatus, systems and methods receive a new firmware image at a memory device and place the new firmware image into second nonvolatile storage locations of the memory device such that the second nonvolatile storage locations do not overlap with first nonvolatile storage locations of the memory device that store a current firmware image. Embodiments place a logical address to physical address mapping for the new firmware image into a remap data structure stored in memory circuits of the memory device. The remap data structure also includes a logical address to physical address mapping for the current firmware image. Embodiments provide a first status value to indicate that the logical address to physical address mapping for the new firmware image is a valid firmware image and a second status value to indicate that the logical address to physical address mapping for the current firmware image is an invalid firmware image.Type: ApplicationFiled: January 6, 2020Publication date: September 24, 2020Applicant: Cypress Semiconductor CorporationInventors: Stephan Rosner, Sergey Ostrikov, Cliff Zitlaw, Yuichi Ise
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Publication number: 20200133887Abstract: An apparatus including non-volatile memory to store a forensic key and data, the data received from a host computing system. A processing device is coupled to the non-volatile memory and is to: allow writing the data, by the host computing system, to a region of the non-volatile memory; in response to a lock signal received from the host computing system, assert a lock on the region of the non-volatile memory, the lock to cause a restriction on access to the region of the non-volatile memory by an external device; and provide unrestricted access, by the external device, to the region of the non-volatile memory in response to verification of the forensic key received from the external device.Type: ApplicationFiled: March 19, 2019Publication date: April 30, 2020Applicant: Cypress Semiconductor CorporationInventors: Avi Avanindra, Stephan Rosner, Cliff Zitlaw
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Patent number: 10613997Abstract: Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.Type: GrantFiled: April 12, 2019Date of Patent: April 7, 2020Assignee: Cypress Semiconductor CorporationInventor: Cliff Zitlaw
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Patent number: 10552145Abstract: A memory device can include a memory cell array and a remap data structure. A remap data structure can include a mapping history section configured to store sets of mappings between logical addresses and the physical addresses of the regions, and a status section configured to identify one of the sets of mappings as a live set for the device. Control logic can be coupled to the memory cell array and the remap data structure and configured to enable access to the storage locations and remap data structure. Firmware update systems and methods, including firmware-over-the-air (FOTA), that include a memory device are also disclosed.Type: GrantFiled: June 11, 2018Date of Patent: February 4, 2020Assignee: Cypress Semiconductor CorporationInventors: Stephan Rosner, Sergey Ostrikov, Cliff Zitlaw, Yuichi Ise
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Publication number: 20190386966Abstract: An apparatus includes a non-volatile memory (NVM) device coupled to a host, the NVM device including a processing device to: receive a communication packet from a server via the host computing system that is coupled to the NVM device and communicatively coupled to the server, the communication packet comprising clear text data that requests to initiate secure communications; perform a secure handshake with the server, via communication through the host computing system, using a secure protocol that generates a session key; receive data, via the host computing system, from the server within a secure protocol packet, wherein the data is inaccessible to the host computing system; authenticate the data using secure protocol metadata of the secure protocol packet; optionally decrypt, using the session key, the data to generate plaintext data; and store the plaintext data in NVM storage elements of the NVM device.Type: ApplicationFiled: June 4, 2019Publication date: December 19, 2019Applicant: Cypress Semiconductor CorporationInventors: Sergey Ostrikov, Stephan Rosner, Cliff Zitlaw
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Publication number: 20190303307Abstract: Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.Type: ApplicationFiled: April 12, 2019Publication date: October 3, 2019Applicant: Cypress Semiconductor CorporationInventor: Cliff Zitlaw
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Publication number: 20190179625Abstract: A memory device can include a memory cell array and a remap data structure. A remap data structure can include a mapping history section configured to store sets of mappings between logical addresses and the physical addresses of the regions, and a status section configured to identify one of the sets of mappings as a live set for the device. Control logic can be coupled to the memory cell array and the remap data structure and configured to enable access to the storage locations and remap data structure. Firmware update systems and methods, including firmware-over-the-air (FOTA), that include a memory device are also disclosed.Type: ApplicationFiled: June 11, 2018Publication date: June 13, 2019Applicant: Cypress Semiconductor CorporationInventors: Stephan Rosner, Sergey Ostrikov, Cliff Zitlaw, Yuichi Ise
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Patent number: 10222989Abstract: Providing for a multi-bank memory with bank-specific status feedback is described herein. By way of example, the multi-bank memory can be configured to output an availability status, pass/fail status, error correction status, or the like, for subsets of multiple memory banks. In some embodiments, the non-volatile memory can provide global status information, representing a status of all banks commonly in conjunction with bank-specific status information. Further, the subject disclosure provides addressing techniques for identifying particular banks of memory, and obtaining status information for subsets of the memory banks, or performing memory operations on targeted subsets of the memory banks.Type: GrantFiled: June 25, 2015Date of Patent: March 5, 2019Assignee: CROSSBAR, INC.Inventor: Cliff Zitlaw