Abstract: In accordance with the invention, an improved image sensor comprises an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques. The germanium elements are subsequently formed overlying the silicon by epitaxial growth. The germanium elements are advantageously grown within surface openings of a dielectric cladding. Wafer fabrication techniques are applied to the elements to form isolated germanium photodiodes. Since temperatures needed for germanium processing are lower than those for silicon processing, the formation of the germanium devices need not affect the previously formed silicon devices. Insulating and metallic layers are then deposited and patterned to interconnect the silicon devices and to connect the germanium devices to the silicon circuits.

Abstract: A high-speed optical communications cell is integrated at the interior of a two-dimensional imaging array. The combined receiver and imager carries out both photodetection (converting photons to electrons) and circuit functions (e.g. amplifying and integrating the signals from the photodetectors). The high-speed receiver cell comprises a photodetector and a high-speed amplification circuit, providing an electrical output which can follow a rapidly varying optical signal falling on the photodetector. The imaging array comprises an array of photodetectors and readout circuits, providing an electrical representation of the variation of light with position across the receiver surface.

Abstract: A block of intermediate transfer material for use in a printing apparatus having an intermediate transfer member, said intermediate transfer member being equipped with a heater to heat said intermediate transfer member to a temperature of at least about 40° C., said intermediate transfer member having a surface with a first shape, a marking material applicator situated to apply marking material in an imagewise pattern to the intermediate transfer member, and a transferring apparatus to transfer the imagewise pattern of marking material to a final recording substrate, said block of intermediate transfer material comprising a silicone polymer containing monomers of the formula wherein R1, R2, R3, R4, R5, x, y, and z are as defined herein, wherein the monomers can be directly bonded to each other or bonded through spacer groups, said block of intermediate transfer material having a surface with a second shape substantially the complement of the first shape.

Abstract: A printing apparatus for applying a marking material to a final substrate, said printing apparatus comprising an intermediate transfer member; an intermediate transfer material applicator for transferring intermediate transfer material from a solid block of intermediate transfer material to form a molten layer of intermediate transfer material on the intermediate transfer member; a marking material applicator situated to apply marking material in an imagewise pattern to the molten layer of intermediate transfer material on the intermediate transfer member; and a transferring apparatus to transfer the imagewise pattern of marking material to a final recording substrate.

Abstract: The present invention provides, in one embodiment, a method of fabricating a heterostructure bipolar transistor. This particular embodiment comprises forming a n-type doped region in a semiconductor substrate to form a collector, epitaxially forming a base on the collector, epitaxially doping the base with indium while forming the base, and forming an emitter on the base. The base is epitaxially formed, and at the same time the base is doped with indium. In other words, the indium is epitaxially incorporated within the base as the base is being formed. In addition to the indium, the base may also be epitaxially doped with boron. Since, indium is incorporated into the base with the same epitaxial process used to form the base, the damage typically associated with conventional implantation processes are not present, and thus, the high annealing temperatures to repair the damage are not required. The base can be doped and formed at the same time; thereby, saving processing time.

Abstract: A heterojunction bipolar transistor in an integrated circuit has intrinsic and extrinsic base portions. The intrinsic base portion substantially comprises epitaxial silicon-germanium alloy. The extrinsic base portion substantially comprises polycrystalline material, and contains a distribution of ion-implanted impurities. An emitter overlies the intrinsic base portion, and a spacer at least partially overlies the emitter. The spacer overhangs the extrinsic base portion by at least a distance characteristic of lateral straggle of the ion-implanted impurities.

Abstract: A method is described for making at least one MOS transistor on a silicon substrate. According to this method, a layer of a silicon dioxide material is formed on a principal surface of the substrate. The oxide layer is then patterned such that at least one source region and at least one drain region of the substrate are exposed. A layer of boron-doped germanium is then deposited on the exposed regions by RTCVD. The substrate is then heated such that boron diffuses from the germanium layer into the source and drain regions. The substrate principal surface can then be etched such that the germanium layer is removed with high selectivity.

Abstract: The present invention comprises a method of fabricating devices and circuits employing at least one heteroepitaxial layer under strain. The thickness of the heteroepitaxial layer is more than two times the calculated equilibrium critical thickness for an uncapped heteroepitaxial layer upon a crystalline substrate, based on previously known equilibrium theory for the uncapped layer. Subsequent to growth of the heteroepitaxial layer, the structure is processed at temperatures higher than the growth temperature of the heteroepitaxial layer.The strained heteroepitaxial layer (second layer) is epitaxially grown upon the surface of a first, underlaying crystalline layer, creating a heterojunction. Subsequently a third crystalline layer is deposited or grown upon the major exposed surface of the second, strained heteroepitaxial layer. The preferred manner of growth of the third crystalline layer is epitaxial growth.

Abstract: The inventive method of making a poly-Si emitter transistor (PET) comprises opening an emitter window in a dielectric (typically SiO.sub.2) layer, and depositing onto the thus exposed surface and/or into the single crystal Si material that underlies the exposed surface at least one atomic species. This deposition step is following by the conventional poly-Si deposition, dopant implantation and "drive-in". In a currently preferred embodiment the novel deposition step comprises a low dose, low energy As implantation (5.times.10.sup.13 -2.times.10.sup.15 atoms/cm.sup.2, 0.1-5 keV). The novel method can result in significantly improved device characteristics, e.g., in a doubling of h.sub.FE, as compared to analogous prior art PETs.

Abstract: Improved devices with silicon to SiGe alloy heterojunctions are provided for in accordance with the following discoveries. X-ray topography and transmission electron microscopy were used to quantify misfit-dislocation spacings in as-grown Si.sub.1-x Ge.sub.x films formed by Limited Reaction Processing (LRP), which is a chemical vapor deposition technique. These analysis techniques were also used to study dislocation formation during annealing of material grown by both LRP and by molecular beam epitaxy (MBE). The thickness at which misfit dislocations first appear in as-grown material was similar for both growth techniques. The thermal stability of capped and uncapped films was also investigated after rapid thermal annealing in the range of 625.degree. to 1000.degree. C. Significantly fewer misfit dislocations were observed in samples containing an epitaxial silicon cap.