Patents by Inventor Clifford A. Zitlaw

Clifford A. Zitlaw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200301856
    Abstract: Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 24, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventor: Clifford Zitlaw
  • Publication number: 20200287716
    Abstract: Disclosed are apparatus and methods for programming a plurality of nonvolatile memory (NVM) devices. Each NVM device self-generates and stores a unique encryption key. Each NVM device concurrently receives an image from a multiple-device programming system to which all the NVM devices are communicatively coupled. Each NVM device encrypts the received image using such NVM device's unique encryption key to produce a unique encrypted image for each NVM device. Each NVM device stores its unique encrypted image within a nonvolatile memory of such NVM device. The unique encryption key can then be securely transferred to a host device for decrypting the image accessed from one of the NVM devices.
    Type: Application
    Filed: December 13, 2019
    Publication date: September 10, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: Clifford Zitlaw, Markus Unseld, Sandeep Krishnegowda, Daisuke Nakata, Shinsuke Okada, Stephan Rosner
  • Patent number: 10338826
    Abstract: Systems and methods embed a random-access non-volatile memory array in a managed-NAND system to execute the boot code or other time-sensitive applications. By embedding this random-access non-volatile memory in the managed-NAND system, either on the memory controller chip or as a separate chip within the managed-NAND system package, an application may be read with fast initial access time, alleviating the slow access time limitations of NAND Flash technology. Depending on the size of the application, the system may be configured to read the whole application content or only a time-critical portion from this embedded random-access non-volatile memory array.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: July 2, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sylvain Dubois, Stephan Rosner, Clifford A. Zitlaw
  • Patent number: 9710191
    Abstract: Data associated with a logical block address (LBA) may be received from a host system to be stored in the memory array. The LBA may be translated to a physical block address (PBA) by determining a first portion of the PBA and a second portion of the PBA. The data from the host system may be stored in the buffer space after determining the first portion of the PBA and before determining the second portion of the PBA. The data from the buffer space may be flushed to the memory array after determining the second portion of the PBA.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: July 18, 2017
    Assignee: MONTEREY RESEARCH, LLC
    Inventors: Frank Edelhaeuser, Clifford A. Zitlaw, Jeremy Mah
  • Patent number: 9524247
    Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment, a fractured erase process is performed in which a pre-program process, erase process and soft program process are initiated independently. Memory cells can be pre-programmed and conditioned independent of an erase command. The initiation of the independent pre-programming is partitioned from an erase command which is partitioned from initiation of a soft-programming command. A cell is erased wherein the erasing includes erase operations that are partitioned from the pre-preprogramming process. In one embodiment, the independent pre-program process is run in the background.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: December 20, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Clifford A. Zitlaw, Hagop Artin Nazarian
  • Patent number: 9317445
    Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a host for processing information, a memory controller and a memory. The memory controller controls communication of the information between the host and the memory, wherein the memory controller routes data rapidly to a buffer of the memory without buffering in the memory controller. The memory stores the information. The memory includes a buffer for temporarily storing the data while corresponding address information is determined.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: April 19, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Frank Edelhaeuser, Clifford A Zitlaw, Jeremy Mah
  • Publication number: 20150169463
    Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment, a fractured erase process is performed in which a pre-program process, erase process and soft program process are initiated independently. Memory cells can be pre-programmed and conditioned independent of an erase command. The initiation of the independent pre-programming is partitioned from an erase command which is partitioned from initiation of a soft-programming command. A cell is erased wherein the erasing includes erase operations that are partitioned from the pre-preprogramming process. In one embodiment, the independent pre-program process is run in the background.
    Type: Application
    Filed: February 24, 2015
    Publication date: June 18, 2015
    Inventors: Clifford A. ZITLAW, Hagop Artin NAZARIAN
  • Patent number: 9047237
    Abstract: Embodiments are directed to reduced power consumption for memory data transfer at high frequency through synchronized clock signaling. Delay locked loop (DLL) circuits are used to generate the synchronized clock signals. A DLL circuit consumes power as long as it is outputting the synchronized clock signals. A power saving apparatus and method are described wherein the DLL circuit is powered on when memory data access is active, while the DLL circuit is powered down when memory access is idle.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: June 2, 2015
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Qamrul Hasan, Clifford Zitlaw, Stephan Rosner, Sylvain Dubois
  • Publication number: 20150106548
    Abstract: Systems and methods embed a random-access non-volatile memory array in a managed-NAND system to execute the boot code or other time-sensitive applications. By embedding this random-access non-volatile memory in the managed-NAND system, either on the memory controller chip or as a separate chip within the managed-NAND system package, an application may be read with fast initial access time, alleviating the slow access time limitations of NAND Flash technology. Depending on the size of the application, the system may be configured to read the whole application content or only a time-critical portion from this embedded random-access non-volatile memory array.
    Type: Application
    Filed: October 15, 2013
    Publication date: April 16, 2015
    Inventors: Sylvain DUBOIS, Stephan Rosner, Clifford Zitlaw
  • Patent number: 8984238
    Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment, a fractured erase process is performed in which a pre-program process, erase process and soft program process are initiated independently. Memory cells can be pre-programmed and conditioned independent of an erase command. The initiation of the independent pre-programming is partitioned from an erase command which is partitioned from initiation of a soft-programming command. A cell is erased wherein the erasing includes erase operations that are partitioned from the pre-preprogramming process. In one embodiment, the independent pre-program process is run in the background.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: March 17, 2015
    Assignee: Spansion LLC
    Inventors: Clifford A. Zitlaw, Hagop Artin Nazarian
  • Publication number: 20140040587
    Abstract: Embodiments are directed to reduced power consumption for memory data transfer at high frequency through synchronized clock signaling. Delay locked loop (DLL) circuits are used to generate the synchronized clock signals. A DLL circuit consumes power as long as it is outputting the synchronized clock signals. A power saving apparatus and method are described wherein the DLL circuit is powered on when memory data access is active, while the DLL circuit is powered down when memory access is idle.
    Type: Application
    Filed: August 3, 2012
    Publication date: February 6, 2014
    Applicant: Spansion LLC
    Inventors: Qamrul HASAN, Clifford ZITLAW, Stephan ROSNER, Sylvain DUBOIS
  • Patent number: 8386736
    Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a host for processing information, a memory controller and a memory. The memory controller controls communication of the information between the host and the memory, wherein the memory controller routes data rapidly to a buffer of the memory without buffering in the memory controller. The memory stores the information. The memory includes a buffer for temporarily storing the data while corresponding address information is determined.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: February 26, 2013
    Assignee: Spansion LLC
    Inventors: Frank Edelhaeuser, Clifford A Zitlaw, Jeremy Mah
  • Patent number: 7774536
    Abstract: A memory device is described that enhances initialization of the memory device. In the prior art, initialization of synchronous Flash memory requires the release of hardware signal line, RP#, or an initialization command, LCR, and a following initialization time wait period of 50 ?S to 100 ?S. The improved memory device of the detailed invention begins initialization of internal values upon acquiring stable power. The initialization cycle of the detailed memory loops and continues until a command is received from the host controller and is immediately available for access. This allows the utilization of the detailed memory in systems wherein the host controller cannot supply an initializing signal (RP# or LCR). The detailed memory also allows for immediate availability of the memory upon issuance of the command allowing for a fast first access.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: August 10, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Clifford Zitlaw, Frankie Fariborz Roohparvar
  • Publication number: 20100199056
    Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment, a fractured erase process is performed in which a pre-program process, erase process and soft program process are initiated independently. Memory cells can be pre-programmed and conditioned independent of an erase command. The initiation of the independent pre-programming is partitioned from an erase command which is partitioned from initiation of a soft-programming command. A cell is erased wherein the erasing includes erase operations that are partitioned from the pre-preprogramming process. In one embodiment, the independent pre-program process is run in the background.
    Type: Application
    Filed: February 5, 2009
    Publication date: August 5, 2010
    Inventors: Clifford A. ZITLAW, Hagop Artin NAZARIAN
  • Publication number: 20100161935
    Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a host for processing information, a memory controller and a memory. The memory controller controls communication of the information between the host and the memory, wherein the memory controller routes data rapidly to a buffer of the memory without buffering in the memory controller. The memory stores the information. The memory includes a buffer for temporarily storing the data while corresponding address information is determined.
    Type: Application
    Filed: December 18, 2008
    Publication date: June 24, 2010
    Inventors: Frank EDELHAEUSER, Clifford A. ZITLAW, Jeremy MAH
  • Publication number: 20060184782
    Abstract: A memory device is described that enhances initialization of the memory device. In the prior art, initialization of synchronous Flash memory requires the release of hardware signal line, RP#, or an initialization command, LCR, and a following initialization time wait period of 50 ?S to 100 ?S. The improved memory device of the detailed invention begins initialization of internal values upon acquiring stable power. The initialization cycle of the detailed memory loops and continues until a command is received from the host controller and is immediately available for access. This allows the utilization of the detailed memory in systems wherein the host controller cannot supply an initializing signal (RP# or LCR). The detailed memory also allows for immediate availability of the memory upon issuance of the command allowing for a fast first access.
    Type: Application
    Filed: April 7, 2006
    Publication date: August 17, 2006
    Inventors: Clifford Zitlaw, Frankie Roohparvar
  • Patent number: 7036004
    Abstract: An improved Flash memory device with a synchronous interface has been detailed that enhances initialization of the Flash memory device. In the prior art, initialization of synchronous Flash memory requires the release of hardware signal line, RP#, or an initialization command, LCR, and a following initialization time wait period of 50 ?S to 100 ?S. The improved Flash memory device of the detailed invention begins initialization of internal values upon acquiring stable power. The initialization cycle of the detailed synchronous Flash memory loops and continues until a “STOP” command is received from the host controller and is immediately available for access. This allows the utilization of the detailed synchronous Flash memory in systems wherein the host controller cannot supply an initializing signal (RP# or LCR). The detailed synchronous Flash memory also allows for immediate availability of the Flash memory upon issuance of the “STOP” command allowing for a fast first access.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: April 25, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Clifford Zitlaw, Frankie Fariborz Roohparvar
  • Publication number: 20050086423
    Abstract: A system and method for implementing a NAND memory interface for an embedded PC system are disclosed. The system and method include a NAND interface device adapted to be coupled to a first chip select of a dedicated SDRAM bus, and at least one NAND memory device coupled to the NAND interface device. The first chip select is utilized to access the NAND memory device via the NAND interface device. Accordingly, the NAND interface device and the at least one NAND memory device function substantially as a hard disk in the embedded PC system. As a result, lower costs for non-volatile memory are achieved while increasing speed and decreasing motherboard PCB real estate requirements.
    Type: Application
    Filed: October 17, 2003
    Publication date: April 21, 2005
    Inventor: Clifford Zitlaw
  • Publication number: 20030023840
    Abstract: An improved Flash memory device with a synchronous interface has been detailed that enhances initialization of the Flash memory device. In the prior art, initialization of synchronous Flash memory requires the release of hardware signal line, RP#, or an initialization command, LCR, and a following initialization time wait period of 50 &mgr;S to 100 &mgr;S. The improved Flash memory device of the detailed invention begins initialization of internal values upon acquiring stable power. The initialization cycle of the detailed synchronous Flash memory loops and continues until a “STOP” command is received from the host controller and is immediately available for access. This allows the utilization of the detailed synchronous Flash memory in systems wherein the host controller cannot supply an initializing signal (RP# or LCR).
    Type: Application
    Filed: July 25, 2001
    Publication date: January 30, 2003
    Applicant: Micron Technology, Inc.
    Inventors: Clifford Zitlaw, Frankie Fariborz Roohparvar
  • Patent number: 5270972
    Abstract: A three-terminal serial-communication peripheral device for low-cost applications is described. The peripheral device comprises a first terminal for receiving a modulated power signal including a source of power and a clocking signal, a second terminal for receiving a reference potential such as a ground reference, and a third terminal for communicating data to and from the peripheral device. The peripheral device further comprises a digital subsystem which exchanges data with an application system. The exchanged data may be stored and retrieved by the digital subsystem, as when the subsystem is a memory unit, or the data may be in the form of measurement data which the peripheral device is supplying to the application system, the measured data being supplied by a sensor of the subsystem. With its three terminals, the peripheral device can communicate data to and from the application system.
    Type: Grant
    Filed: April 14, 1992
    Date of Patent: December 14, 1993
    Assignee: Xicor, Inc.
    Inventors: Gary M. Craig, Clifford A. Zitlaw