Patents by Inventor Clifford Cooper

Clifford Cooper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11768770
    Abstract: Described apparatuses and methods order memory address portions advantageously for cache-memory addressing. An address bus can have a smaller width than a memory address. The multiple bits of the memory address can be separated into most-significant bits (MSB) and least-significant bits (LSB) portions. The LSB portion is provided to a cache first. The cache can process the LSB portion before the MSB portion is received. The cache can use index bits of the LSB portion to index into an array of memory cells and identify multiple corresponding tags. The cache can also check the corresponding tags against lower tag bits of the LSB portion. A partial match may be labeled as a predicted hit, and a partial miss may be labeled as an actual miss, which can initiate a data fetch. With the remaining tag bits from the MSB portion, the cache can confirm or refute the predicted hit.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: September 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Joseph Thomas Pawlowski, Elliott Clifford Cooper-Balis, David Andrew Roberts
  • Publication number: 20230061668
    Abstract: Described apparatuses and methods order memory address portions advantageously for cache-memory addressing. An address bus can have a smaller width than a memory address. The multiple bits of the memory address can be separated into most-significant bits (MSB) and least-significant bits (LSB) portions. The LSB portion is provided to a cache first. The cache can process the LSB portion before the MSB portion is received. The cache can use index bits of the LSB portion to index into an array of memory cells and identify multiple corresponding tags. The cache can also check the corresponding tags against lower tag bits of the LSB portion. A partial match may be labeled as a predicted hit, and a partial miss may be labeled as an actual miss, which can initiate a data fetch. With the remaining tag bits from the MSB portion, the cache can confirm or refute the predicted hit.
    Type: Application
    Filed: August 30, 2022
    Publication date: March 2, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Joseph Thomas Pawlowski, Elliott Clifford Cooper-Balis, David Andrew Roberts
  • Patent number: 11436144
    Abstract: Described apparatuses and methods order memory address portions advantageously for cache-memory addressing. An address bus can have a smaller width than a memory address. The multiple bits of the memory address can be separated into most-significant bits (MSB) and least-significant bits (LSB) portions. The LSB portion is provided to a cache first. The cache can process the LSB portion before the MSB portion is received. The cache can use index bits of the LSB portion to index into an array of memory cells and identify multiple corresponding tags. The cache can also check the corresponding tags against lower tag bits of the LSB portion. A partial match may be labeled as a predicted hit, and a partial miss may be labeled as an actual miss, which can initiate a data fetch. With the remaining tag bits from the MSB portion, the cache can confirm or refute the predicted hit.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Joseph Thomas Pawlowski, Elliott Clifford Cooper-Balis, David Andrew Roberts
  • Publication number: 20210318958
    Abstract: Described apparatuses and methods order memory address portions advantageously for cache-memory addressing. An address bus can have a smaller width than a memory address. The multiple bits of the memory address can be separated into most-significant bits (MSB) and least-significant bits (LSB) portions. The LSB portion is provided to a cache first. The cache can process the LSB portion before the MSB portion is received. The cache can use index bits of the LSB portion to index into an array of memory cells and identify multiple corresponding tags. The cache can also check the corresponding tags against lower tag bits of the LSB portion. A partial match may be labeled as a predicted hit, and a partial miss may be labeled as an actual miss, which can initiate a data fetch. With the remaining tag bits from the MSB portion, the cache can confirm or refute the predicted hit.
    Type: Application
    Filed: April 10, 2020
    Publication date: October 14, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Joseph Thomas Pawlowski, Elliott Clifford Cooper-Balis, David Andrew Roberts
  • Patent number: 10591979
    Abstract: Techniques for battery management of a device having multiple batteries are described herein. In one or more implementations, management for increased battery reliability involves assessing a combination of factors that influence a control policy for multiple batteries in a battery system. Based on the assessment, values of control parameters for power management of the battery system are set to reflect a tradeoff between performance and reliability. Then, at least one of battery utilization or charge current distribution is controlled in dependence upon the values that are set. Control of the battery system can be based in part upon differences in cycle counts for multiple batteries of a battery system for a device, such that cycle counts of the multiple batteries are managed for improved reliability.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: March 17, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Karan Kacker, Daniel Joseph Dummer, Wei Guo, Stephen Clifford Cooper, Ceceli Ann Wilhelmi, Minsoo Kim
  • Patent number: 9763826
    Abstract: The guide (2) consists of a positioning member (16) that enables a user to align an eye drop dispenser bottle (4) with the eye to be treated. The guide (2) includes an attachment device (6) for removably attaching the guide (2) to the eye drop dispenser bottle (4) and two arms (14) connected to the attachment device (6) by a pair of multiple use living hinges (12). The positioning member (16) bridges the two arms (14) and is rotatable between a stowed position and an operational position, such that when in the operational position the positioning member (16) is arranged between the eye drop dispenser bottle (4) and the eye to be treated. The guide (2) further comprises a locking arrangement (18, 20) for locking the guide (2) in the operational position.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: September 19, 2017
    Inventor: Clifford Cooper
  • Publication number: 20160291683
    Abstract: Techniques for battery management of a device having multiple batteries are described herein. In one or more implementations, management for increased battery reliability involves assessing a combination of factors that influence a control policy for multiple batteries in a battery system. Based on the assessment, values of control parameters for power management of the battery system are set to reflect a tradeoff between performance and reliability. Then, at least one of battery utilization or charge current distribution is controlled in dependence upon the values that are set. Control of the battery system can be based in part upon differences in cycle counts for multiple batteries of a battery system for a device, such that cycle counts of the multiple batteries are managed for improved reliability.
    Type: Application
    Filed: April 3, 2015
    Publication date: October 6, 2016
    Inventors: Karan Kacker, Daniel Joseph Dummer, Wei Guo, Stephen Clifford Cooper, Ceceli Ann Wilhelmi, Minsoo Kim
  • Publication number: 20150351960
    Abstract: The guide (2) consists of a positioning member (16) that enables a user to align an eye drop dispenser bottle (4) with the eye to be treated. The guide (2) includes an attachment device (6) for removably attaching the guide (2) to the eye drop dispenser bottle (4) and two arms (14) connected to the attachment device (6) by a pair of multiple use living hinges (12). The positioning member (16) bridges the two arms (14) and is rotatable between a stowed position and an operational position, such that when in the operational position the positioning member (16) is arranged between the eye drop dispenser bottle (4) and the eye to be treated. The guide (2) further comprises a locking arrangement (18, 20) for locking the guide (2) in the operational position.
    Type: Application
    Filed: January 7, 2014
    Publication date: December 10, 2015
    Inventor: Clifford COOPER
  • Patent number: 6821399
    Abstract: An apparatus for cathodic arc coating. The apparatus includes: a vacuum chamber which includes: an anode; a power supply; and a cathode target assembly connected to the power supply. The cathode target assembly includes a cathode target having an interference fit stud with a threadless distal end. In the preferred embodiment, the distal end of the threadless cathode target also includes a pre-determined surface texture and a cooling block in contact with the cathode target.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: November 23, 2004
    Assignee: General Electric Company
    Inventors: Scott Andrew Weaver, Don Mark Lipkin, Reed Roeder Corderman, Terry Clifford Cooper
  • Patent number: 6608432
    Abstract: An apparatus for cathodic arc coating. The apparatus includes: a vacuum chamber which includes an anode; a power supply; and a cathode target assembly connected to the power supply. The cathode target assembly includes a cathode target and a target holder. In the preferred embodiment, a conductive interlayer is located between the cathode target and the target holder, and a cooling block is in contact with the cathode target.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: August 19, 2003
    Assignee: General Electric Company
    Inventors: Scott Andrew Weaver, Don Mark Lipkin, Reed Roeder Corderman, Terry Clifford Cooper
  • Publication number: 20020144893
    Abstract: An apparatus for cathodic arc coating. The apparatus includes: a vacuum chamber which includes: an anode; a power supply; and a cathode target assembly connected to the power supply. The cathode target assembly includes a cathode target having an interference fit stud with a threadless distal end. In the preferred embodiment, the distal end of the threadless cathode target also includes a pre-determined surface texture and a cooling block in contact with the cathode target.
    Type: Application
    Filed: May 2, 2002
    Publication date: October 10, 2002
    Inventors: Scott Andrew Weaver, Don Mark Lipkin, Reed Roeder Corderman, Terry Clifford Cooper
  • Publication number: 20020140334
    Abstract: An apparatus for cathodic arc coating. The apparatus includes: a vacuum chamber which includes an anode; a power supply; and a cathode target assembly connected to the power supply. The cathode target assembly includes a cathode target and a target holder. In the preferred embodiment, a conductive interlayer is located between the cathode target and the target holder, and a cooling block is in contact with the cathode target.
    Type: Application
    Filed: April 3, 2001
    Publication date: October 3, 2002
    Applicant: General Electric Company
    Inventors: Scott Andrew Weaver, Don Mark Lipkin, Reed Roeder Corderman, Terry Clifford Cooper
  • Patent number: 6457482
    Abstract: A portable power-cleaning device for use with commonly available containers includes a pulsation device consisting of an electric motor with a shaft, an eccentric weight attached to the motor shaft, a speed control for the motor, and a mount that connects the motor to an adjustable bracket. A clamp or strap attaches the adjustable bracket to a container, and a cover protects the user from contact with the motor, electronic controls, and the eccentric weight.
    Type: Grant
    Filed: October 18, 2000
    Date of Patent: October 1, 2002
    Inventor: John Clifford Cooper
  • Patent number: 6436254
    Abstract: An apparatus for cathodic arc coating. The apparatus includes: a vacuum chamber which includes: an anode; a power supply; and a cathode target assembly connected to the power supply. The cathode target assembly includes a cathode target having an interference fit stud with a threadless distal end. In the preferred embodiment, the distal end of the threadless cathode target also includes a pre-determined surface texture and a cooling block in contact with the cathode target.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: August 20, 2002
    Assignee: General Electric Company
    Inventors: Scott Andrew Weaver, Don Mark Lipkin, Reed Roeder Corderman, Terry Clifford Cooper
  • Patent number: 4915422
    Abstract: A joint to be used with a coupling tool for coupling first and second axially aligned hubless pipe end sections. The joint includes an outer sleeve and an inner liner disposed within the outer sleeve. A pair of diametrically opposed cylindrically shaped lugs are positioned on the outer surface of the outer sleeve. The axis of each lug is oriented perpendicularly to the longitudinal axis of the outer sleeve for mating engagement with a slot formed in the coupling tool. The pipe end sections are retained by compression of the liner in abutting relationship with a lip formed on the interior surface of the outer sleeve. The lugs are positioned equidistant from the axial ends of the outer sleeve for insertion of the pipe end sections easily within either axial end of the sleeve.
    Type: Grant
    Filed: January 6, 1989
    Date of Patent: April 10, 1990
    Assignee: The American Brass & Iron Foundry
    Inventors: Michael Chacon, Clifford Cooper, Michael Herrell, John Fehringer, Daniel Nunes, Joseph Panek, Theodore Ray, Anthony Sumida, Clifford Wixson