Abstract: A vertical, FinFET device includes an array of FinFETs comprising a plurality of rows and columns of fins. Each of the fins has a fin length and a fin width, a first fin tip, a second fin tip, and a central region disposed between the first fin tip of a first row of the plurality of rows and the second fin tip of a second row of the plurality of rows. The central region is characterized by an electrical conductivity. The FinFET device also includes a neutralized region including the first fin tip, a region between the first row of the plurality of rows and the second row of the plurality of rows, and the second fin tip. The neutralized region is characterized by a second electrical conductivity less than the electrical conductivity of the central region. The FinFET device further includes an electrical conductor disposed over the neutralized region.

Abstract: A vertical fin-based field effect transistor (FinFET) device includes an array of FinFETs comprising a plurality of rows and columns of fins, each of the fins having a fin length and a fin width measured laterally with respect to the fin length and including a first fin tip disposed at a first end of the fin; a second fin tip disposed at a second end of the fin opposing the first end; a bridging structure connecting the first fin tip to an adjacent fin; a central region disposed between the first fin tip and the second fin tip and characterized by an electrical conductivity; and a source contact electrically coupled to the central region. The FinFET device also includes a gate region surrounding the fins.

Abstract: A vertical, FinFET device includes an array of FinFETs comprising a plurality of rows and columns of fins. Each of the fins has a fin length and a fin width, a first fin tip, a second fin tip, and a central region disposed between the first fin tip of a first row of the plurality of rows and the second fin tip of a second row of the plurality of rows. The central region is characterized by an electrical conductivity. The FinFET device also includes a neutralized region including the first fin tip, a region between the first row of the plurality of rows and the second row of the plurality of rows, and the second fin tip. The neutralized region is characterized by a second electrical conductivity less than the electrical conductivity of the central region. The FinFET device further includes an electrical conductor disposed over the neutralized region.

Abstract: A method of forming regrown fiducials includes providing a III-V compound substrate having a device region and an alignment mark region. The III-V compound substrate is characterized by a processing surface. The method also includes forming a hardmask layer having a first set of openings in the device region exposing a first surface portion of the processing surface of the III-V compound substrate and a second set of openings in the alignment mark region exposing a second surface portion of the processing surface and etching the first surface portion and the second surface portion of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches. The method also includes epitaxially regrowing a semiconductor layer in the trenches to form the regrown fiducials extending to a predetermined height over the processing surface in the alignment mark region.

Abstract: A gallium nitride (GaN) power device includes a GaN substrate structure having a first surface and a second surface, a metallic layer coupled to the second surface of the GaN substrate structure, and an active region including an array of vertical fin-based field effect transistors (FinFETs) coupled to the GaN substrate structure. The GaN power device also includes an edge termination structure circumscribing the active region and a seal ring structure circumscribing the edge termination structure and comprising a seal ring metal pad operable to conduct charge from the edge termination structure to the metallic layer.

Abstract: A method of fabricating a semiconductor device includes providing a substrate structure comprising a semiconductor substrate of a first conductivity type, a drift layer on the semiconductor substrate, and a fin array on the drift layer and surrounded by a recess region. The fin array comprises a first row of fins and a second row of fins parallel to each other and separated from each other by a space. The first row of fins comprises a plurality of first elongated fins extending parallel to each other in a first direction. The second row of fins comprises a plurality of second elongated fins extending parallel to each other in a second direction parallel to the first direction. The method also includes epitaxially regrowing a gate layer surrounding the first and second row of fins on the drift layer and filling the recess region.

Abstract: A vertical fin-based field effect transistor (FinFET) device includes an array of FinFETs comprising a plurality of rows and columns of separated fins. Each of the separated fins has a length and a width measured laterally with respect to the length and includes a first fin tip disposed at a first end of the separated fin, a second fin tip disposed at a second end of the separated fin opposing the first end, a central region disposed between the first fin tip and the second fin tip and characterized by a first electrical conductivity, and a source contact electrically coupled to the central region. The first fin tip and the second fin tip are characterized by a second electrical conductivity less than the first electrical conductivity. The FinFET further includes a first gate region surrounding the first fin tip and a second gate region surrounding the second fin tip.

Abstract: A method of forming alignment marks, each alignment mark including a plurality of fiducials, includes providing a III-V compound substrate having a device region and an alignment mark region. The method also includes forming a first hardmask in the device region and a hardmask structure in the alignment mark region, etching a first surface portion of the III-V compound substrate to form a plurality of trenches in the device region, and epitaxially regrowing a semiconductor layer in the trenches. The method further includes forming a second mask in the device region and a patterned structure in the alignment mark region. The patterned structure includes a set of masked regions corresponding to the plurality of fiducials and a second set of openings. The method also includes forming the plurality of fiducials.

Abstract: A method of manufacturing a vertical FET device includes providing a semiconductor substrate structure including a marker layer; forming a hardmask layer coupled to the semiconductor substrate structure, wherein the hardmask layer comprises a set of openings operable to expose an upper surface portion of the semiconductor substrate structure; etching the upper surface portion of the semiconductor substrate structure to form a plurality of fins; etching at least a portion of the marker layer; detecting the etching of the at least a portion of the marker layer; epitaxially growing a semiconductor layer in recess regions disposed between adjacent fins of the plurality of fins; forming a source metal layer on each of the plurality of fins; and forming a gate metal layer coupled to the semiconductor layer.

Abstract: A method of forming alignment marks includes providing a III-V compound substrate having a device region and an alignment mark region, forming a hardmask layer having a first set of openings on the alignment mark region exposing a first surface portion of the III-V compound substrate and a second set of openings on the device region exposing a second surface portion of the III-V compound substrate, etching the exposed surface of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches, and epitaxially regrowing a semiconductor layer in the trenches to form the alignment marks extending to a predetermined height over the processing surface of the III-V compound substrate.

Abstract: Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.

Abstract: A vertical, fin-based field effect transistor (FinFET) device includes an array of individual FinFET cells. The array includes a plurality of rows and columns of separated fins. Each of the separated fins is in electrical communication with a source contact. The vertical FinFET device also includes one or more rows of first inactive fins disposed on a first set of sides of the array of individual FinFET cells, one or more columns of second inactive fins disposed on a second set of sides of the array of individual FinFET cells, and a gate region surrounding the individual FinFET cells of the array of individual FinFET cells, the first inactive fins, and the second inactive fins.

Abstract: A III-N-based vertical transistor includes a III-N substrate, a source, a drain, and a channel comprising a III-N crystal material and extending between the source and the drain. The channel includes at least one sidewall surface aligned ±0.3° with respect to an m-plane of the III-N crystal material. The III-N-based vertical transistor also includes a gate electrically coupled to the at least one sidewall surface of the channel.

Abstract: A semiconductor device includes an active device region and a plurality of guard rings arranged in a first concentric pattern surrounding the active device region. The semiconductor device also includes a plurality of junctions arranged in a second concentric pattern surrounding the active device region. At least one of the plurality of junctions is arranged between two adjacent guard rings of the plurality of guard rings, and the plurality of junctions have a different resistivity than the plurality of guard rings. The semiconductor device further includes a plurality of coupling paths. At least one of the plurality of coupling paths is arranged to connect two adjacent guard rings of the plurality of guard rings.

Abstract: A method for manufacturing a semiconductor device includes: providing a semiconductor substrate; epitaxially growing a first semiconductor layer coupled to the semiconductor substrate; epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer comprises a contact region and a terminal region surrounding the contact region; forming a mask layer on the second semiconductor layer, wherein the mask layer is patterned with a tapered region aligned with the terminal region of the second semiconductor layer; implanting ions into the terminal region of the second semiconductor layer using the mask layer to form a tapered junction termination element in the terminal region of the second semiconductor layer; and forming a contact structure in the contact region of the second semiconductor layer.

Abstract: A method of clamping a voltage includes providing a fin-based field effect transistor (FinFET) device. The FinFET device includes an array of FinFETs. Each FinFET includes a source contact electrically coupled to a fin and a gate contact. The method also includes applying the voltage to the source contact and applying a second voltage to the gate contact. The voltage is greater than the second voltage. The method further includes increasing the voltage to a threshold voltage and conducting current from the source contact to the gate contact in response to the voltage reaching the threshold voltage.

Abstract: A vertical MOSFET includes a substrate and a first III-nitride layer of a first conductivity type and having a first dopant concentration coupled to the substrate. First trenches are within the first III-nitride layer. A second III-nitride structure of a second dopant concentration and a second conductivity type opposite to the first conductivity type are within the first trenches. A third III-nitride layer of the second conductivity type is coupled to the first III-nitride layer and the second III-nitride structure. A fourth III-nitride layer of the first conductivity type coupled to the third III-nitride layer. Second trenches are within the third and fourth III-nitride layers. A gate dielectric and a gate conductor are within the second trenches. A source conductor is coupled to an upper portion of the fourth III-nitride layer. The first III-nitride layer and the second III-nitride structure provide a charge balance structure.

Abstract: A semiconductor device includes an active device region and a plurality of guard rings arranged in a first concentric pattern surrounding the active device region. The semiconductor device also includes a plurality of junctions arranged in a second concentric pattern surrounding the active device region. At least one of the plurality of junctions is arranged between two adjacent guard rings of the plurality of guard rings, and the plurality of junctions have a different resistivity than the plurality of guard rings. The semiconductor device further includes a plurality of coupling paths. At least one of the plurality of coupling paths is arranged to connect two adjacent guard rings of the plurality of guard rings.

Abstract: A method of fabricating a vertical fin-based field effect transistor (FET) includes providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type, epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a graded doping layer on the drift layer, and epitaxially growing a second semiconductor layer having the first conductivity type on the graded doping layer. The method also includes forming a metal compound layer on the second semiconductor layer, forming a patterned hard mask layer on the metal compound layer, and etching the metal compound layer and the second semiconductor layer using the patterned hard mask layer as a mask exposing a surface of the graded doping layer to form a plurality of fins surrounded by a trench.

Abstract: A method for manufacturing a semiconductor device includes: providing a semiconductor substrate; epitaxially growing a first semiconductor layer coupled to the semiconductor substrate; epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer comprises a contact region and a terminal region surrounding the contact region; forming a mask layer on the second semiconductor layer, wherein the mask layer is patterned with a tapered region aligned with the terminal region of the second semiconductor layer; implanting ions into the terminal region of the second semiconductor layer using the mask layer to form a tapered junction termination element in the terminal region of the second semiconductor layer; and forming a contact structure in the contact region of the second semiconductor layer.