Patents by Inventor Clifford Fishley

Clifford Fishley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7804167
    Abstract: An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: September 28, 2010
    Assignee: LSI Logic Corporation
    Inventors: Clifford Fishley, Abiola Awujoola, Leonard Mora, Amar Amin, Maurice Othieno, Chok J. Chia
  • Publication number: 20080128919
    Abstract: An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.
    Type: Application
    Filed: December 1, 2006
    Publication date: June 5, 2008
    Inventors: Clifford Fishley, Abiola Awujoola, Leonard Mora, Amar Amin, Maurice Othieno, Chok J. Chia
  • Publication number: 20050104172
    Abstract: A carrier substrate includes an access region placed within the interior of the substrate that facilitates backside access to an integrated circuit die without damaging electrical integrity of the carrier substrate, a ring of die connection pads placed around the access region, and an array of package connection pads positioned around the perimeter of the top surface of the carrier substrate. In one embodiment, the perimeter depth of the array of package connections pads is selected to correspond to the number of electrical traces routable between minimally spaced package connection pads. The basic carrier substrate design is used to create an integrated circuit carrier family with each particular circuit carrier configured to receive a range of integrated circuit sizes and I/O counts such that each circuit carrier overlaps in size range with at least one other circuit carrier.
    Type: Application
    Filed: November 14, 2003
    Publication date: May 19, 2005
    Applicant: LSI LOGIC CORPORATION
    Inventors: Abiola Awujoola, Clifford Fishley
  • Publication number: 20050104164
    Abstract: A package shell that is electrically and thermally conductive is placed over an integrated circuit die and associated wire-bond connections to electromagnetically shield the resulting integrated circuit package. The package shell is attached to the top surface of a substrate bearing the integrated circuit die and is electrically connected to a grounding path. The package shell may be filled with a thermally conductive filler in order to increase the heat dissipation and EMI shielding of the resulting integrated circuit package.
    Type: Application
    Filed: November 14, 2003
    Publication date: May 19, 2005
    Applicant: LSI LOGIC CORPORATION
    Inventors: Abiola Awujoola, Clifford Fishley
  • Patent number: 6540467
    Abstract: A system and a method are provided for preventing damage to wafers arranged in a wafer cassette. In particular, an apparatus is provided to protect wafers arranged in a wafer cassette during insertion of a wafer into the cassette. In one embodiment, the apparatus may be a separate entity from the wafer cassette. In this manner, the apparatus may be situated about the cassette such that the wafers arranged in the cassette are protected during insertion of a wafer. In another embodiment, the wafer cassette itself may be adapted to partially cover and protect the wafers arranged in the cassette during insertion of a wafer. Consequently, a method is provided using either embodiment of the apparatus. In particular, the method may include inserting a wafer into a wafer cassette by shielding one or more slots of the cassette, exposing a designated slot of the cassette, and inserting a wafer into the designated slot.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: April 1, 2003
    Assignee: LSI Logic Corporation
    Inventors: Nael O. Zohni, Clifford Fishley