Abstract: The Intelligent Multiservice Access System (IMAS) enables support for the next generation of virtual connections. Regardless of whether the communications lines coupled to the inputs and outputs of the IMAS are based on SVC, PVC, or a combination of PVC and SVC, the IMAS can support SVCs for a more flexible, timely, efficient, and manageable connection. In the more typical configuration, the loop side of the IMAS is PVC-based because the modems do not support SVC signaling, and the telecommunications backbone side is capable of supporting SVC signaling even though existing DSLAMs do not employ SVC signaling logic. With SVC support, the IMAS assists the ATM network in hand crafting an SVC-based connection almost immediately between end users when the originating end user wants to make a call to a destination end user, and tear down that virtual connection almost immediately when that call has completed.

Abstract: The Intelligent Multiservice Access System (IMAS) enables support for the next generation of virtual connections. Regardless of whether the communications lines coupled to the inputs and outputs of the IMAS are based on SVC, PVC, or a combination of PVC and SVC, the IMAS can support SVCs for a more flexible, timely, efficient, and manageable connection. In the more typical configuration, the loop side of the IMAS is PVC-based because the modems do not support SVC signaling, and the telecommunications backbone side is capable of supporting SVC signaling even though existing DSLAMs do not employ SVC signaling logic. With SVC support, the IMAS assists the ATM network in hand crafting an SVC-based connection almost immediately between end users when the originating end user wants to make a call to a destination end user, and tear down that virtual connection almost immediately when that call has completed.

Abstract: An efficient, cost effective method and apparatus for performing resource allocation of available bit rate (ABR) virtual circuit (VC) in an asynchronous transfer mode (ATM) network includes an explicit rate switch process performed at at least one switch of an ABR VC. The process provides a fast and more accurate computation of the number of active VCs in an ATM network. Furthermore, the fair share allocation is calculated at the switch in a way that is efficient and lends itself easily to implementation in hardware. For example, in one embodiment, the fair share is implemented using a series of counters and registers controlled by a state machine. This simple hardware implementation enables fast convergence to a current final state so that timely accurate resource utilization and allocation to the ABR VCs can be determined.

Abstract: Reactive congestion control in an asynchronous transfer mode (ATM) network where the network is formed by the interconnection of nodes each including a forward path for transfer of information from source to destination through the network and a return path for returning congestion control signals. Each source includes a modifiable issue rate unit which issues forward information signals at different rates for virtual channels in response to the presence and absence of congestion signals received on the return path.