Abstract: A distributed processing network is disclosed. The network includes at least one network switch, coupled to one or more end nodes, and adapted to simultaneously receive and route a plurality of data packets between the one or more end nodes. Within the network, the one or more end nodes are interconnected by one or more communication links adapted to provide a predetermined level of fault tolerant error detection and recovery.

Abstract: Systems and methods for global memory for a RapidIO network are provided. In one embodiment, a method for accessing global data on a RapidIO network comprises obtaining ownership of a global memory unit (GMU) and receiving a data write packet at a GMU endpoint on a RapidIO network. The data write packet includes a source network identifier and a dataset. The method further comprises verifying whether the source network identifier matches a lock owner network identifier stored in a first register, and verifying one or both of whether one or both of a processor endpoint and a controller endpoint are permitted to alter the lock owner network identifier, and whether the source network identifier identifies a processor endpoint authorized to write data on the GMU based on a set of authorized source network identifiers stored in a second register. The method further comprises storing the dataset on the GMU.

Abstract: Methods and systems for refresh and error scrubbing of dynamic memory devices is provided. A method for maintaining the integrity of data stored in dynamic memory devices comprises determining a refresh-scrub-access-period time interval for a dynamic memory device having a plurality of memory elements, based on a refresh rate requirement for the dynamic memory device and an error scrub rate requirement; and performing an error-scrub function on each memory element of the dynamic memory device at a periodicity not exceeding the refresh-scrub-access-period time interval.