Patents by Inventor Clifford L. Ong
Clifford L. Ong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071913Abstract: An integrated circuit structure includes a first interconnect layer, and a second interconnect layer above the first interconnect layer. The first interconnect layer includes a first interconnect feature and a second interconnect feature. The second interconnect layer includes a third interconnect feature, a fourth interconnect feature, and a fifth interconnection feature. The third interconnect feature extends from an upper surface of the first interconnect feature to an upper surface of the second interconnect layer. In an example, the fourth interconnect feature extends from an upper surface of the second interconnect feature to below the upper surface of the second interconnect layer, and the fifth interconnect feature extends from an upper surface of the fourth interconnect feature to the upper surface of the second interconnect layer. Thus, a double-decked vertical stack of interconnect features is formed using the fourth interconnect feature within the second interconnect layer.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Applicant: Intel CorporationInventors: June Choi, Richard Schenker, Charles H. Wallace, Nikhil J. Mehta, Clifford L. Ong
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Publication number: 20230328947Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.Type: ApplicationFiled: June 14, 2023Publication date: October 12, 2023Inventors: Zheng GUO, Clifford L. ONG, Eric A. KARL, Mark T. BOHR
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Patent number: 11737253Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.Type: GrantFiled: June 22, 2017Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Zheng Guo, Clifford L. Ong, Eric A. Karl, Mark T. Bohr
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Publication number: 20230084182Abstract: Techniques are provided herein to form semiconductor devices having a different number of semiconductor nanoribbons compared to other semiconductor devices on the same substrate. In one example, two different semiconductor devices of a given memory cell, such as a random access memory (RAM) cell, include a p-channel device and an n-channel device. More specifically, the p-channel device may be a GAA transistor with a first number of semiconductor nanoribbons while the n-channel device may be a GAA transistor with a second number of semiconductor nanoribbons that is greater than the first number of semiconductor nanoribbons. In some cases, the n-channel device(s) have one additional semiconductor nanoribbon compared to the p-channel device(s). Depending on when the nanoribbons are removed during the fabrication process, different structural outcomes will occur that can be detected in the final device.Type: ApplicationFiled: September 13, 2021Publication date: March 16, 2023Applicant: Intel CorporationInventors: Mohammad Hasan, Tahir Ghani, Pratik A. Patel, Mohit K. Haran, Leonard P. Guler, Clifford L. Ong
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Publication number: 20230079586Abstract: Techniques are provided herein to form semiconductor devices having thinned semiconductor regions (e.g., thinner nanoribbons) compared to other semiconductor devices on the same substrate and at a comparable height (e.g., within same layer or adjacent layers). In an example, neighboring semiconductor devices of a given memory cell include a p-channel device and an n-channel device. The p-channel device may be a GAA transistor with a semiconductor nanoribbon having a first width while the n-channel device may be a GAA transistor with a semiconductor nanoribbon having a second width that is larger than the first width (e.g., first width is half the second width). The p-channel device may have a thinner width than the corresponding n-channel device in order to structurally lower the operating current through the p-channel devices by decreasing the width of the active semiconductor channel.Type: ApplicationFiled: September 13, 2021Publication date: March 16, 2023Applicant: Intel CorporationInventors: Mohammad Hasan, Tahir Ghani, Pratik A. Patel, Leonard P. Guler, Mohit K. Haran, Clifford L. Ong
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Patent number: 10957386Abstract: An apparatus is provided which comprises: an interconnect comprising poly extending in a first direction; a power supply rail extending in a second direction, wherein the second direction is parallel to the first direction; and a memory array organized in rows and columns, wherein the rows are orthogonal to the columns, wherein the first and second directions are parallel to the rows of the memory array, wherein the memory array comprises bit-cells (e.g., 6T SRAM bit-cells) that are organized such that there are no gap bit-cells in the array.Type: GrantFiled: March 23, 2020Date of Patent: March 23, 2021Assignee: Intel CorporationInventors: Zheng Guo, Clifford L. Ong, Eric A. Karl
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Publication number: 20200286549Abstract: An apparatus is provided which comprises: an interconnect comprising poly extending in a first direction; a power supply rail extending in a second direction, wherein the second direction is parallel to the first direction; and a memory array organized in rows and columns, wherein the rows are orthogonal to the columns, wherein the first and second directions are parallel to the rows of the memory array, wherein the memory array comprises bit-cells (e.g., 6T SRAM bit-cells) that are organized such that there are no gap bit-cells in the array.Type: ApplicationFiled: March 23, 2020Publication date: September 10, 2020Applicant: Intel CorporationInventors: Zheng Guo, Clifford L. Ong, Eric A. Karl
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Patent number: 10600476Abstract: An apparatus is provided which comprises: an interconnect comprising poly extending in a first direction; a power supply rail extending in a second direction, wherein the second direction is parallel to the first direction; and a memory array organized in rows and columns, wherein the rows are orthogonal to the columns, wherein the first and second directions are parallel to the rows of the memory array, wherein the memory array comprises bit-cells (e.g., 6T SRAM bit-cells) that are organized such that there are no gap bit-cells in the array.Type: GrantFiled: March 1, 2018Date of Patent: March 24, 2020Assignee: Intel CorporationInventors: Zheng Guo, Clifford L. Ong, Eric A. Karl
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Publication number: 20200058656Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.Type: ApplicationFiled: June 22, 2017Publication date: February 20, 2020Inventors: Zheng GUO, Clifford L. ONG, Eric A. KARL, Mark T. BOHR
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Publication number: 20190272868Abstract: An apparatus is provided which comprises: an interconnect comprising poly extending in a first direction; a power supply rail extending in a second direction, wherein the second direction is parallel to the first direction; and a memory array organized in rows and columns, wherein the rows are orthogonal to the columns, wherein the first and second directions are parallel to the rows of the memory array, wherein the memory array comprises bit-cells (e.g., 6T SRAM bit-cells) that are organized such that there are no gap bit-cells in the array.Type: ApplicationFiled: March 1, 2018Publication date: September 5, 2019Applicant: Intel CorporationInventors: Zheng Guo, Clifford L. Ong, Eric A. Karl
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Patent number: 8362806Abstract: Provided is a novel keeper circuit with a pull-up device whose strength changes for different operating supply levels so that the pull-up device is weaker for smaller supply levels and stringer for higher supply levels.Type: GrantFiled: June 26, 2009Date of Patent: January 29, 2013Assignee: Intel CorporationInventors: Sapumal B. Wijeratne, Clifford L. Ong, Hans J. Greub, Anandraj Devarajan
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Publication number: 20100327909Abstract: Provided is a novel keeper circuit with a pull-up device whose strength changes for different operating supply levels so that the pull-up device is weaker for smaller supply levels and stringer for higher supply levels.Type: ApplicationFiled: June 26, 2009Publication date: December 30, 2010Inventors: Sapumal B. Wijeratne, Clifford L. Ong, Hans J. Greub, Anandraj Devarajan