Abstract: A buffer deadlock prevention technique for dataflow computations. The invention that implements the following algorithm: (1) providing a supplemental buffer for each input of a "downstream" program; (2) partitioning the inputs of each downstream program into disjoint input sets, such that two inputs are in the same input set if and only if such inputs come, either directly or indirectly, from a common upstream program; (3) attempting to read data into a downstream program from an "upstream" program via an input I in an input set; (4) if no data is currently available from input I, and if any other input J in the same input set has data available, then reading into the downstream program available data from each such input J and storing such that data in the supplemental buffer corresponding to such input J until such time as available data is exhausted on all such inputs J or data becomes available on input I.

Abstract: A method and apparatus by which a graph can be used to invoke computations directly. Methods get information into and out of individual processes represented on a graph, move information between the processes, and define a running order for the processes. An application writer informs a system incorporating the invention how processes should access necessary data. The invention adds "adaptor processes", if necessary, to assist in getting information into and out of processes.

Abstract: A method and system that applies transaction techniques to file system operations in non-database applications executing on parallel processing systems. For each of a set of file operations, methods embodied in program routines are defined for performing, finalizing, and undoing the operations, so that the operations may be used in a non-database application to create a transaction processing environment. In general, in one aspect, the invention provides a computer program library for adding the semantics of transactions to a set of native operations of a native file system.

Abstract: The present invention provides a parallel vector machine model for building a compiler that exploits three different levels of parallelism found in a variety of parallel processing machines, and in particular, the Connection Machine.RTM. Computer CM-2 system. The fundamental idea behind the parallel vector machine model is to have a target machine that has a collection of thousands of vector processors each with its own interface to memory. Thus allowing a fine-grained array-based source program to be mapped onto a course-grained hardware made up of the vector processors. In the parallel vector machine model used by CM Fortran 1.0, the FPUs, their registers, and the memory hiearchy are directly exposed to the compiler. Thus, the CM-2 target machine is not 64K simple bit-serial processors. Rather, the target is a machine containing 2K PEs (processing elements), where each PE is both superpipelined and superscalar. The compiler uses data distribution to spread the problem out among the 2K processors.

Abstract: A virtual processor mechanism and specific techniques and instructions for utilizing such virtual processor mechanism within an SIMD computer having numerous processors, and each physical processor having dedicated memory associated therewith. Each physical processor is used to simulate multiple "virtual" processors, with each physical processor simulating the same number of virtual processors. The memory of each physical processor is divided into n regions of equal size, each such region being allocated to one virtual processor, where n is the number of virtual processors simulated by each physical processor. Whenever an instruction is processed, each physical processor is time-sliced among the virtual memory regions, performing the operation first as one virtual processor, then another, until the operation has been performed for all virtual processors. Physical processors are switched among the virtual processors in a completely regular, predictable, deterministic fashion.

Abstract: A method is described for simulating additional processors in a SIMD computer by dividing the memory associated with each processor into a plurality of sub-memories and then operating on each sub-memory in succession as if it were associated with a separate processor. Thus, a first instruction or set of instructions is applied to all the processors of the array to cause at least some processors to process data stored at a first location or locations in the first sub-memory. Thereafter, the same first instruction or set of instructions is applied to all the processors of the array to cause at least some processors to process data stored at the same first location in a second sub-memory. And so forth for each of the sub-memories. By operating a SIMD computer in this fashion, it is possible in effect to vary the number of processors in the array so as to provide the number of processors required for a problem.