Abstract: Provided, in one embodiment, is an integrated circuit (IC) leadframe. In one example, the leadframe includes a paddle, wherein the paddle has a surface configured to accept an IC chip and has at least one edge, the at least one edge having one or more slots located therein. In this example, the leadframe may further include a plurality of lead fingers having ends extending toward the at least one edge, wherein the ends of ones of pairs of adjacent lead fingers extend into corresponding slots in the paddle.

Abstract: Provided, in one embodiment, is an integrated circuit (IC) leadframe. In one example, the leadframe includes a paddle, wherein the paddle has a surface configured to accept an IC chip and has at least one edge. In this example, the leadframe may further include a plurality of lead fingers having ends extending toward the at least one edge, wherein the ends of ones of adjacent lead fingers are staggered proximate and distal the at least one edge.

Abstract: An electronic device includes an integrated circuit (IC) die attached to a substrate, and electrical conductors connecting the IC die to the substrate. The electronic device also includes a heat spreader located over the IC die and having a concaved portion located over the IC die along with a lateral portion extending from the concaved portion. The lateral portion has a surface area greater than a surface area of the concaved portion. A support member is further included that extends from the lateral portion to and contacts the substrate. An encapsulant covers the support member leaving the lateral and concaved portions exposed on outer sides thereof. In another aspect, a method of manufacturing an electronic device is also included.

Abstract: A die package generally including (A) ground paths routing a power ground from a ground power set of contact pads in a first conductive layer to a ground ring in a second conductive layer, (B) core paths routing a core voltage from a core power set of contact pads in the first conductive layer to a core ring in the second conductive layer, and (C) input/output voltage paths routing input/output voltages from an input/output power set of contact pads in the first conductive layer to an input/output ring in the second conductive layer, (i) the input/output ring surrounding the core ring, (ii) the ring being configured to power input and output circuits of the die, (iii) the input/output ring being split into ring segments isolated from each other and (iv) at least one particular ring segment having a length of less than a single connector pitch.

Abstract: A die package generally including (A) ground paths routing a power ground from a ground power set of contact pads in a first conductive layer to a ground ring in a second conductive layer, (B) core paths routing a core voltage from a core power set of contact pads in the first conductive layer to a core ring in the second conductive layer, and (C) input/output voltage paths routing input/output voltages from an input/output power set of contact pads in the first conductive layer to an input/output ring in the second conductive layer, (i) the input/output ring surrounding the core ring, (ii) the ring being configured to power input and output circuits of the die, (iii) the input/output ring being split into ring segments isolated from each other and (iv) at least one particular ring segment having a length of less than a single connector pitch.

Abstract: A carrier substrate includes an access region placed within the interior of the substrate that facilitates backside access to an integrated circuit die without damaging electrical integrity of the carrier substrate, a ring of die connection pads placed around the access region, and an array of package connection pads positioned around the perimeter of the top surface of the carrier substrate. In one embodiment, the perimeter depth of the array of package connections pads is selected to correspond to the number of electrical traces routable between minimally spaced package connection pads. The basic carrier substrate design is used to create an integrated circuit carrier family with each particular circuit carrier configured to receive a range of integrated circuit sizes and I/O counts such that each circuit carrier overlaps in size range with at least one other circuit carrier.

Abstract: A heat spreader for use with an integrated circuit in a package, where the heat spreader is formed as a plate having a centrally disposed aperture with a diameter that is smaller than a minimum diameter of the integrated circuit. The heat spreader has an overall diameter that is no greater than a minimum diameter of the package. In this manner, the aperture in the heat spreader allows the plastic injected through a top gated mold form to pass through the heat spreader and more uniformly encapsulate the integrated circuit.

Abstract: A configurable package for mounting an integrated circuit to a circuit board. The package has a substrate for receiving the integrated circuit. On the substrate are contacts for making electrical connections between the substrate and the integrated circuit. The substrate also has solder balls for making electrical connections between the substrate and the circuit board. Each one of the contacts is in electrical contact with one each of the solder balls. A clip ring/dam ring overlays and attaches to the substrate. The clip ring/dam ring forms a reservoir for receiving the integrated circuit on the substrate. Also, formed at the periphery of the clip ring/dam ring, are clamping tabs. The reservoir can be filled with an encapsulating material, such as epoxy, to complete the package. A lid is provided for covering the integrated circuit. A clip overlays the lid and releasably attaches to the clamping tabs of the insert, and retains the lid to the insert.