Abstract: An efficient broadband amplifier. The amplifier includes a mechanism for amplifying an input signal via a high-speed switch and providing an amplified signal in response thereto. Another mechanism filters the amplified signal via common mode rejection and provides an output signal in response thereto. In a specific embodiment, the mechanism for filtering includes a first mechanism for separating an input signal into plural intermediate signals. The mechanism for amplifying includes a second mechanism for amplifying the plural intermediate signals via one or more high-speed switches and providing plural amplified signals in response thereto. The mechanism for filtering further includes a third mechanism for employing common mode rejection to filter the plural amplified signals, yielding a single output signal in response thereto.

Abstract: An Advanced Digital Antenna Module (ADAM) for receiving and exciting electromagnetic signals. The ADAM ASIC integrates a complete receiver/exciter function on a monolithic SiGe device, enabling direct digital-to-RF (Radio Frequency) and RF-to-digital transformations. The invention includes an improved analog-to-digital converter (ADC) (10) with a novel active offset method for comparators. The novel ADC architecture (10) includes a first circuit (12, 14) for receiving an input signal; a second circuit (18) for setting a predetermined number of thresholds using a predetermined number of preamplifiers (60) with weighted unit current sources (66) in each of the preamplifier outputs; and a third circuit (20) for comparing the input to the thresholds. In the preferred embodiment, the ADC (10) includes trimmable current sources (66). The ADC (10) of the present invention also includes an improved comparator circuit (62).

Abstract: An Advanced Digital Antenna Module (ADAM) for receiving and exciting electromagnetic signals. The ADAM ASIC integrates a complete receiver/exciter function on a monolithic SiGe device, enabling direct digital-to-RF (Radio Frequency) and RF-to-digital transformations. The invention includes an improved analog-to-digital converter (ADC) (10) with a novel active offset method for comparators. The novel ADC architecture (10) includes a first circuit (12, 14) for receiving an input signal; a second circuit (18) for setting a predetermined number of thresholds using a predetermined number of preamplifiers (60) with weighted unit current sources (66) in each of the preamplifier outputs; and a third circuit (20) for comparing the input to the thresholds. In the preferred embodiment, the ADC (10) includes trimmable current sources (66). The ADC (10) of the present invention also includes an improved comparator circuit (62).

Abstract: A mixed technology microcircuit including a first circuit fabricated on a first layer with a first technology and a second circuit fabricated on a second layer with a second technology. In the illustrative embodiment, the first circuit is fabricated with silicon germanium (SiGe) technology and the second circuit is fabricated with complementary metal-oxide semiconductor (CMOS) technology. In an illustrative application, the first circuit includes a high-speed data receiver and a high-speed data transmitter. In the illustrative implementation, the data receiver includes a line receiver, a data and clock recovery circuit, and a demultiplexer and the data transmitter includes a multiplexer, a data and clock encoding circuit, and a line driver.

Abstract: A mixed technology microcircuit including a first circuit fabricated on a first layer with a first technology and a second circuit fabricated on a second layer with a second technology. In the illustrative embodiment, the first circuit is fabricated with silicon germanium (SiGe) technology and the second circuit is fabricated with complementary metal-oxide semiconductor (CMOS) technology. In an illustrative application, the first circuit includes a high-speed data receiver and a high-speed data transmitter. In the illustrative implementation, the data receiver includes a line receiver, a data and clock recovery circuit, and a demultiplexer and the data transmitter includes a multiplexer, a data and clock encoding circuit, and a line driver.

Abstract: A low cost electrical network analyzer that provides waveform predictions in the time domain of a device for any electrical signal stimuli and with any load. In a preferred embodiment, input, output and stimulating source waveform recorders are used to record tables of time domain data (voltage waveforms) derived by stimulating the device under test with and without an output load coupled thereto. The tables of time domain data are representative of input and output signatures of the device. The tables are stored in a processor and are processed by way of a computer-implemented time domain network analyzer to produce sets of complex parameters as a function of time that are representative of the device. The parameters thus comprise a model of the analyzed device.

Abstract: Three independent signal sources are used to statistically derive the power spectral density of the phase noise content of signals from each of them. This is accomplished by mixing each of the signals two at a time (i.e., signal one with signal two, signal one with signal three, and signal two with signal three) and capturing the resultant difference signals, such as with a waveform recorder, for example. A servo electronics loop is used to remove the carrier and any long term signal drift from the resultant difference signals. Statistical analysis is then used to compute the composite power spectral densities of the the resultant difference signals, and to solve for the individual power spectral densities of the original signals. The present system and method uses the mathematical relationships between the three sources that have similar magnitudes of phase noise, to compute the power spectral density of the noise content of signals from each source.

Abstract: Linear signal reconstruction systems and methods that use mathematical relationships that exist between discrete time signals, digital to analog conversion characteristics and digital signal processing to produce a highly accurate, low noise, arbitrary analog signal from a discrete digital representation. This analog signal is produced by connecting discrete digital voltages through the use of a segmented straight line curve fit. This approach significantly reduces out of band harmonics that are normally associated with the stair-step approach while improving the output signal amplitude and phase accuracy. More specifically, the present system and method provides for reconstructing original analog signals from a digitized representation thereof. Digitized signals corresponding to the original analog signals are differentiated and then D to A converted into differentiated analog signals.

Abstract: An automated process and device for testing both C.W. and swept output signal modulation of a system or unit under test. The invention conditions the output signals to be compatible for measurement, measures incremental cycle periods of the signals using a continuous time counter, converts raw signal data into formatted tables, calculates prescribed parameters relating to the signals, aligns the calculated prescribed parameters relating to the signals, computes incremental signal frequencies from the incremental cycle periods as measured, substarts the incremental signal frequencies from the predicted signal frequencies to form a frequency residual model, constructs a curve using the incremental signal frequencies, and displays the curve. A prediction model is created and used to predict expected results. The prediction model defines ideal behavior of both C.W. and swept signals from a unit under test.