Abstract: A synchronous serial communication link between a controller and a peripheral is resynchronized by the sending of a series of bits at a first logic level by the controller. The series of bits is long enough to ensure that the peripheral will decode a command word in which all of the bits are at the first logic level. The peripheral, upon decoding such a command word, resets the synchronization circuitry within the peripheral. The controller then sends a single bit of the opposite logic state followed by serial data. The peripheral, upon receipt of this bit of the opposite logic state, releases the synchronization circuitry from its reset condition and begins to decode the serial data in synchronization with the controller.