Patents by Inventor Clint A. Hardy

Clint A. Hardy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200004625
    Abstract: Provided are a computer program product, system, and method for using a machine learning module to determine when to perform error checking of a storage unit. Input on attributes of at least one storage device comprising the storage unit are provided to a machine learning module to produce an output value. An error check frequency is determined from the output value. A determination is made as to whether the error check frequency indicates to perform an error checking operation with respect to the storage unit. The error checking operation is performed in response to determining that the error checking frequency indicates to perform the error checking operation.
    Type: Application
    Filed: August 14, 2018
    Publication date: January 2, 2020
    Inventors: Matthew G. Borlick, Karl A. Nielsen, Clint A. Hardy, Lokesh M. Gupta
  • Patent number: 10521139
    Abstract: Copy source to target operations may be selectively and preemptively undertaken in advance of source destage operations. In another aspect, logic detects sequential writes including large block writes to point-in-time copy sources. In response, destage tasks on the associated point-in-time copy targets are started which include in one embodiment, stride-aligned copy source to target operations which copy unmodified data from the point-in-time copy sources to the point-in-time copy targets in alignment with the strides of the target. As a result, when write data of write operations is destaged to the point-in-time copy sources, such source destages do not need to wait for copy source to target operations since they have already been performed. In addition, the copy source to target operations may be stride-aligned with respect to the stride boundaries of the point-in-time copy targets. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: December 31, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Clint A. Hardy, Karl A. Nielsen
  • Patent number: 10521147
    Abstract: One general aspect of device reservation state synchronization in accordance with the present description, device reservation management logic ensures synchronization of reservation states of primary and secondary volumes of a mirror relationship in the event of a change in the state of the mirroring relationship such as achieving full data synchronization between the volumes. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 31, 2019
    Assignee: International Business Machines Corporation
    Inventors: Scott B. Compton, Matthew R. Craig, Clint A. Hardy, Matthew J. Kalos, Carol S. Mellgren, John G. Thompson
  • Publication number: 20190354497
    Abstract: Provided are a computer program product, system, and method for using at least one machine learning module to select a priority queue from which to process an Input/Output (I/O) request. Input I/O statistics are provided on processing of I/O requests at the queues to at least one machine learning module. Output is received from the at least one machine learning module for each of the queues. The output for each queue indicates a likelihood that selection of an I/O request from the queue will maintain desired response time ratios between the queues. The received output for each of the queues is used to select a queue of the queues. An I/O request from the selected queue is processed.
    Type: Application
    Filed: August 1, 2018
    Publication date: November 21, 2019
    Inventors: Karl A. Nielsen, Clint A. Hardy, Lokesh M. Gupta, Matthew G. Borlick
  • Publication number: 20190354496
    Abstract: Provided are a computer program product, system, and method for using at least one machine learning module to select a priority queue from which to process an Input/Output (I/O) request. Input I/O statistics are provided on processing of I/O requests at the queues to at least one machine learning module. Output is received from the at least one machine learning module for each of the queues. The output for each queue indicates a likelihood that selection of an I/O request from the queue will maintain desired response time ratios between the queues. The received output for each of the queues is used to select a queue of the queues. An I/O request from the selected queue is processed.
    Type: Application
    Filed: May 18, 2018
    Publication date: November 21, 2019
    Inventors: Karl A. Nielsen, Clint A. Hardy, Lokesh M. Gupta, Matthew G. Borlick
  • Publication number: 20190332457
    Abstract: Provided are a computer program product, system, and method for managing I/O requests to a storage array of storage devices in a machine having a processor node and device adaptor. In response to initiating a rebuild of data in the storage array, the device adaptor determines whether a remaining fault tolerance at the storage array comprises a non-zero fault tolerance that permits at least one further storage device to fail and still allow recovery of data stored in the storage array. In response to determining that the remaining fault tolerance is a zero fault tolerance that does not permit at least one storage device to fail and allow recovery of data, the device adaptor sends a message to the processor node to cause the processor node to initiate an emergency protocol to terminate a mission critical operation when the processor node is performing the mission critical operation.
    Type: Application
    Filed: July 10, 2019
    Publication date: October 31, 2019
    Inventors: Clint A. HARDY, Matthew G. BORLICK, Adrian C. GERHARD, Lokesh M. GUPTA
  • Publication number: 20190303015
    Abstract: Provided are a computer program product, system, and method for sharing alias addresses among logical devices for a control unit managing access by hosts to logical devices configured with capacity from attached physical devices. An alias management group of logical devices and alias addresses assigned to the logical devices is configured. A plurality of requests to establish an association of the host with a logical device and the alias addresses assigned to the logical devices in the alias management group are received from a host. Acknowledgment is made to the host that the association is established in response to determining that the host is assigned the logical devices and alias addresses of the logical devices in the alias management group. The host can use one available alias address assigned to any one of the logical devices to access any one of the logical devices indicated in the association.
    Type: Application
    Filed: June 19, 2019
    Publication date: October 3, 2019
    Inventors: Susan K. Candelaria, Scott B. Compton, Matthew R. Craig, Clint A. Hardy, Matthew J. Kalos, Dale F. Riedy, Richard A. Ripberger, Harry M. Yudenfriend
  • Publication number: 20190286344
    Abstract: Provided are a computer program product, system, and method for sharing alias addresses among logical devices by a host accessing logical devices provisioned with a capacity from physical devices managed by a control unit. The host establishes with the control unit an association of logical devices and alias addresses assigned to the logical devices, wherein the alias addresses are associated with an alias management group. Alias address pool information is generated indicating each of the logical devices and their assigned alias addresses indicated in the association. The host uses from the alias address pool information any one of the alias addresses in the alias address pool information to access any of the logical devices associated with the same alias management group as the alias address.
    Type: Application
    Filed: May 31, 2019
    Publication date: September 19, 2019
    Inventors: Susan K. Candelaria, Scott B. Compton, Matthew R. Craig, Clint A. Hardy, Matthew J. Kalos, Dale F. Riedy, Richard A. Ripberger, Harry M. Yudenfriend
  • Patent number: 10417069
    Abstract: Provided are a computer program product, system, and method for managing I/O requests to a storage array of storage devices in a machine having a processor node and device adaptor. In response to initiating a rebuild of data in the storage array, the device adaptor determines whether a remaining fault tolerance at the storage array comprises a non-zero fault tolerance that permits at least one further storage device to fail and still allow recovery of data stored in the storage array. In response to determining that the remaining fault tolerance is a zero fault tolerance that does not permit at least one storage device to fail and allow recovery of data, the device adaptor sends a message to the processor node to cause the processor node to initiate an emergency protocol to terminate a mission critical operation when the processor node is performing the mission critical operation.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: September 17, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Clint A. Hardy, Matthew G. Borlick, Adrian C. Gerhard, Lokesh M. Gupta
  • Patent number: 10402123
    Abstract: Provided are a computer program product, system, and method for sharing alias addresses among logical devices for a control unit managing access by hosts to logical devices configured with capacity from attached physical devices. An alias management group of logical devices and alias addresses assigned to the logical devices is configured. A plurality of requests to establish an association of the host with a logical device and the alias addresses assigned to the logical devices in the alias management group are received from a host. Acknowledgment is made to the host that the association is established in response to determining that the host is assigned the logical devices and alias addresses of the logical devices in the alias management group. The host can use one available alias address assigned to any one of the logical devices to access any one of the logical devices indicated in the association.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: September 3, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Susan K. Candelaria, Scott B. Compton, Matthew R. Craig, Clint A. Hardy, Matthew J. Kalos, Dale F. Riedy, Richard A. Ripberger, Harry M. Yudenfriend
  • Publication number: 20190258408
    Abstract: A plurality of extents of a plurality of logical volumes are stored in a plurality of ranks, where each logical volume of the plurality of logical volumes is comprised of a plurality of extents including a first extent. In response to determining that first extents stored in each rank of the plurality of ranks have become unbalanced in number in the plurality of ranks, a balancing of the first extents in the plurality of ranks is performed by redistributing the first extents in the plurality of ranks.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Inventors: Clint A. Hardy, Karl A. Nielsen, Qiang Xie, Hui Zhang
  • Publication number: 20190258424
    Abstract: Provided are a computer program product, system, and method for using a delay timer to delay code load operations to process queued write requests. A code load is performed to a selected storage device in a storage array comprised of a plurality of the storage devices. Writes are queued to the storage array in a non-volatile storage while performing the code load. A determination is made as to whether the queued writes to the storage array exceed a threshold. A delay timer is started in response to determining that the queued writes to the storage array exceed the threshold. An additional code load is initiated to an additional selected storage device in the storage array in response to determining that the delay timer has expired. The additional code load is initiated to the additional selected storage device in response to determining that the queued writes are less than the threshold.
    Type: Application
    Filed: February 20, 2018
    Publication date: August 22, 2019
    Inventors: Brian A. Rinaldi, Clint A. Hardy, Samantha A. Utter, Kevin J. Ash, Karl A. Nielsen, Matthew J. Kalos
  • Publication number: 20190243564
    Abstract: Embodiments of the present disclosure may relate to methods and a computer program product for allowing writes based on a granularity level. The method for a storage server may include receiving a received granularity level for a particular volume of a storage device of a client computer including an effective duration for the received granularity level. The method may include receiving an anticipated write to the particular volume at an anticipated write granularity level. The method may include verifying whether the anticipated write granularity level substantially matches the received granularity level at the effective duration. The method may also include writing, in response to the anticipated write granularity level substantially matching the received granularity level at the effective duration, the anticipated write to the particular volume for the received granularity level.
    Type: Application
    Filed: April 15, 2019
    Publication date: August 8, 2019
    Inventors: Juan A. Coronado, Lisa R. Martinez, Beth A. Peterson, Clint A. Hardy, Jennifer S. Shioya
  • Publication number: 20190220370
    Abstract: One general aspect of device reservation state preservation in accordance with the present description, provides for an intermediate reservation state, referred to herein as a “peer” reservation state, which may be maintained by a storage controller in the event of a total loss of communication connectivity to the reserving host so long as a peer or partner storage controller of a mirror relationship still has communication connectivity to the host. The peer reservation state as used herein, is a reservation state intermediate between a full reservation state for a device, and a fully released state in which a reservation of the device has been completely released. Other features and aspects may be realized, depending upon the particular application.
    Type: Application
    Filed: March 26, 2019
    Publication date: July 18, 2019
    Inventors: Scott B. Compton, Matthew R. Craig, Clint A. Hardy, Matthew J. Kalos, Carol S. Mellgren, John G. Thompson
  • Patent number: 10346061
    Abstract: Embodiments of the present disclosure may relate to methods and a computer program product for allowing writes based on a granularity level. The method for a storage server may include receiving a received granularity level for a particular volume of a storage device of a client computer including an effective duration for the received granularity level. The method may include receiving an anticipated write to the particular volume at an anticipated write granularity level. The method may include verifying whether the anticipated write granularity level substantially matches the received granularity level at the effective duration. The method may also include writing, in response to the anticipated write granularity level substantially matching the received granularity level at the effective duration, the anticipated write to the particular volume for the received granularity level.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Juan A. Coronado, Lisa R. Martinez, Beth A. Peterson, Clint A. Hardy, Jennifer S. Shioya
  • Publication number: 20190187921
    Abstract: Copy source to target operations may be selectively and preemptively undertaken in advance of source destage operations. In another aspect, logic detects sequential writes including large block writes to point-in-time copy sources. In response, destage tasks on the associated point-in-time copy targets are started which include in one embodiment, stride-aligned copy source to target operations which copy unmodified data from the point-in-time copy sources to the point-in-time copy targets in alignment with the strides of the target. As a result, when write data of write operations is destaged to the point-in-time copy sources, such source destages do not need to wait for copy source to target operations since they have already been performed. In addition, the copy source to target operations may be stride-aligned with respect to the stride boundaries of the point-in-time copy targets. Other features and aspects may be realized, depending upon the particular application.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 20, 2019
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Clint A. Hardy, Karl A. Nielsen
  • Publication number: 20190187920
    Abstract: Copy source to target operations may be selectively and preemptively undertaken in advance of source destage operations. In another aspect, logic detects sequential writes including large block writes to point-in-time copy sources. In response, destage tasks on the associated point-in-time copy targets are started which include in one embodiment, stride-aligned copy source to target operations which copy unmodified data from the point-in-time copy sources to the point-in-time copy targets in alignment with the strides of the target. As a result, when write data of write operations is destaged to the point-in-time copy sources, such source destages do not need to wait for copy source to target operations since they have already been performed. In addition, the copy source to target operations may be stride-aligned with respect to the stride boundaries of the point-in-time copy targets. Other features and aspects may be realized, depending upon the particular application.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 20, 2019
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Clint A. Hardy, Karl A. Nielsen
  • Patent number: 10324662
    Abstract: A plurality of extents of a plurality of logical volumes are stored in a plurality of ranks, where each logical volume of the plurality of logical volumes is comprised of a plurality of extents including a first extent. In response to determining that first extents stored in each rank of the plurality of ranks have become unbalanced in number in the plurality of ranks, a balancing of the first extents in the plurality of ranks is performed by redistributing the first extents in the plurality of ranks.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Clint A. Hardy, Karl A. Nielsen, Qiang Xie, Hui Zhang
  • Publication number: 20190179719
    Abstract: Provided are a computer program product, system, and method for generating a health condition message on a health condition detected at a first server to send to a host system accessing the first server. A determination is made of a health condition with respect to access to a first storage. A determination is made of an estimated Input/Output (I/O) delay to access the first storage resulting from the determined health condition. A health condition message is generated indicating the estimated I/O delay. The health condition message is transmitted to the host system, wherein the host system uses the estimated I/O delay to determine whether to perform a swap operation to redirect host I/O requests to data from the first server to a second server.
    Type: Application
    Filed: February 20, 2019
    Publication date: June 13, 2019
    Inventors: Clint A. Hardy, Matthew J. Kalos
  • Publication number: 20190171451
    Abstract: Provided are a computer program product, system, and method for reducing a rate at which requests are sent from one processor to another to reduce processor utilization at the processor receiving the requests. A determination is made as to whether processor utilization at the first processor exceeds a utilization threshold. If so, a determination is made as to whether a specified operation is in progress in response to determining that the processor utilization at the first processor exceeds the utilization threshold. The first processor sends a message to the second processor to cause the second processor to reduce a rate at which requests are transferred from the second processor to the first processor in response to determining that the specified operations is in progress.
    Type: Application
    Filed: December 1, 2017
    Publication date: June 6, 2019
    Inventors: Clint A. HARDY, Matthew G. BORLICK, Adrian C. GERHARD, Lokesh M. GUPTA