Abstract: Variable phase bit sampling implementations are disclosed which minimize requirements for downstream digital processing resynchronization in systems that incorporate adjustable bit phase sampling that utilize variable delay elements which can interrupt the clocking stream signal. A sampling device includes a sampling circuit operative to provide an output signal in response to a data signal, where the sampling circuit includes a data input and a clock input. A variable delay circuit provides an adjustable trigger signal to the clock input in response to a first delay control signal. A fixed delay circuit delays the output signal by a predetermined amount of time in response to at least one delay control signal.

Abstract: A signal analysis circuit includes a sampling circuit operative to sample the characteristics of an input signal at various points within a bit window in response to a sample clock signal. A sampling control circuit is coupled to the sampling circuit and is operative to provide the sample clock signal in response to a sample control signal. The sample clock signal provides a variable time function such that the input signal characteristics may be sampled at several times during the input signal or bit window period. A control circuit is coupled to the sampling circuit and the sampling control circuit, and is operative to provide the sample control signal in response to the number of times the input signal is within a signal characteristic of interest. In an exemplary embodiment, the characteristic of interest is a reference pattern that may be synchronized with the input data signal.

Abstract: A signal analysis circuit includes a sampling circuit operative to sample the characteristics of an input signal at various points within a bit window in response to a sample clock signal. A sampling control circuit is coupled to the sampling circuit and is operative to provide the sample clock signal in response to a sample control signal. The sample clock signal provides a variable time function such that the input signal characteristics may be sampled at several times during the input signal or bit window period. A control circuit is coupled to the sampling circuit and the sampling control circuit, and is operative to provide the sample control signal in response to the number of times the input signal is within a signal characteristic of interest. In an exemplary embodiment, the characteristic of interest is a reference pattern that may be synchronized with the input data signal.

Abstract: Variable phase bit sampling implementations are disclosed which minimize requirements for downstream digital processing resynchronization in systems that incorporate adjustable bit phase sampling that utilize variable delay elements which can interrupt the clocking stream signal. A sampling device includes a sampling circuit operative to provide an output signal in response to a data signal, where the sampling circuit includes a data input and a clock input. A variable delay circuit provides an adjustable trigger signal to the clock input in response to a first delay control signal. A fixed delay circuit delays the output signal by a predetermined amount of time in response to at least one delay control signal.

Abstract: Variable phase bit sampling implementations are disclosed which minimize requirements for downstream digital processing resynchronization in systems that incorporate adjustable bit phase sampling that utilize variable delay elements which can interrupt the clocking stream signal. A sampling device includes a sampling circuit operative to provide an output signal in response to a data signal, where the sampling circuit includes a data input and a clock input. A variable delay circuit provides an adjustable trigger signal to the clock input in response to a first delay control signal. A fixed delay circuit delays the output signal by a predetermined amount of time in response to at least one delay control signal.