Abstract: A semiconductor structure may include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide threshold voltage variation in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may only include the first high-k material embedded in the gate dielectric layer. The semiconductor structure may only include the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.

Abstract: A Vertical Field Effect Transistor (VFET) and/or a one transistor dynamic random access memory 1T DRAM that has a substrate with a horizontal substrate surface, a source disposed on the horizontal substrate surface, a drain, and a channel. The channel has a channel top, a channel bottom, a first channel side, a second channel side, and two channel ends. The channel top is connected to the drain. The channel bottom is connected to the source. The channel is vertical and perpendicular to the substrate surface. A first gate stack interfaces with the first channel side and a second gate stack interfaces with the second channel side. A single external gate connection electrically connects the first gate stack and the second gate stack A gate bias (voltage) applied on the single external gate connection biases the first channel side in accumulation and biases the second channel side in inversion. The first gate stack is made of a first high-k dielectric layer and a first gate metal layer.

Abstract: A semiconductor structure may include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide threshold voltage variation in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may only include the first high-k material embedded in the gate dielectric layer. The semiconductor structure may only include the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.

Abstract: A semiconductor structure may include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide threshold voltage variation in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may only include the first high-k material embedded in the gate dielectric layer. The semiconductor structure may only include the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.

Abstract: A semiconductor structure may include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide threshold voltage variation in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may only include the first high-k material embedded in the gate dielectric layer. The semiconductor structure may only include the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.

Abstract: A Vertical Field Effect Transistor (VFET) and/or a one transistor dynamic random access memory 1T DRAM that has a substrate with a horizontal substrate surface, a source disposed on the horizontal substrate surface, a drain, and a channel. The channel has a channel top, a channel bottom, a first channel side, a second channel side, and two channel ends. The channel top is connected to the drain. The channel bottom is connected to the source. The channel is vertical and perpendicular to the substrate surface. A first gate stack interfaces with the first channel side and a second gate stack interfaces with the second channel side. A single external gate connection electrically connects the first gate stack and the second gate stack A gate bias (voltage) applied on the single external gate connection biases the first channel side in accumulation and biases the second channel side in inversion. The first gate stack is made of a first high-k dielectric layer and a first gate metal layer.