Abstract: Ring packet built-in self-test (PBIST) circuitry configured to detect errors in wires connecting a ring of superconducting chips includes circuitry configured to make the PBIST immune to interchip latency and still allow the PBIST to test a stop-to-stop connection. By making a PBIST independent of latency, an entire ring can be characterized for latency and for its bit-error rate prior to running any functional test. Such systems and associated methods can be scaled to larger platforms having any number of ring stops. The PBIST circuitry can function as either transmitter or receiver, or both, to test an entire ring. The PBIST can also be used to tune clocks in the ring to achieve the lowest overall bit error rate (BER) in the ring.

Abstract: Ring packet built-in self-test (PBIST) circuitry configured to detect errors in wires connecting a ring of superconducting chips includes circuitry configured to make the PBIST immune to interchip latency and still allow the PBIST to test a stop-to-stop connection. By making a PBIST independent of latency, an entire ring can be characterized for latency and for its bit-error rate prior to running any functional test. Such systems and associated methods can be scaled to larger platforms having any number of ring stops. The PBIST circuitry can function as either transmitter or receiver, or both, to test an entire ring. The PBIST can also be used to tune clocks in the ring to achieve the lowest overall bit error rate (BER) in the ring.

Abstract: The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one embodiment, a sequence of hard-coded and/or quasi-programmable tests is executed during a BIST routine by receiving test ordering information for the sequence of tests and executing the sequence of tests in an order indicated by the test ordering information. A corresponding BIST circuit comprises a storage element and a state machine. The storage element is configured to store test ordering information for the sequence of tests. The state machine is configured to execute the sequence of tests in an order indicated by the test ordering information.

Abstract: Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching.

Abstract: The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one embodiment, a sequence of hard-coded and/or quasi-programmable tests is executed during a BIST routine by receiving test ordering information for the sequence of tests and executing the sequence of tests in an order indicated by the test ordering information. A corresponding BIST circuit comprises a storage element and a state machine. The storage element is configured to store test ordering information for the sequence of tests. The state machine is configured to execute the sequence of tests in an order indicated by the test ordering information.

Abstract: During a Built-In Self-Test (BIST) routine, execution of a sequence of tests is re-initiated after a corrective action is taken starting with the test having the highest re-ordered priority. The test having the highest re-ordered priority corresponds to a test in a sequence of tests that detected the error corresponding to the corrective action taken or a related test in the case where the test that detected the error is dependent upon results generated by the related test. According to one embodiment, a BIST routine is executed by initiating execution of a sequence of tests configured to detect errors and, after a corrective action is taken in response to one or more of the errors being detected, re-initiating execution of the sequence of tests starting with the test that detected the error corresponding to the corrective action most recently taken.

Abstract: Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching.