Abstract: A bias voltage generator (12) provides a bias control voltage that is connected to a gate of transistor (32) to sink a predetermined amount of bias current. The bias voltage generator (12) is also connected to a gate of a transistor (31) to limit the voltage to a selected bit-line within an array of flash EEPROM cells (26). The predetermined bias current is summed with the current from a selected flash EEPROM cell (46). A reference current generator portion (22), establishes both a reference current and a reference voltage at a second input to a differential amplifier (35). A current-voltage (I-V) characteristic curve of the reference voltage at the second input of the differential amplifier is approximately symmetrically located between the I-V characteristic curves of a flash EEPROM cell when the logic state of the flash EEPROM cell is in an erased state and a programmed state.

Abstract: Zener diodes that are formed concurrently with flash EEPROM cells are utilized to regulate programming voltages for programming a flash EEPROM cell (37). A selected bit-line (38) is voltage regulated with both a zener diode (19) and a bias transistor (36). The bias transistor is activated during programming to prevent breaking down a drain junction of a flash EEPROM cell, which would generate hot-electrons and cause a runaway programming problem. The regulated voltage on the bit-line is also utilized to optimize programming characteristics of a flash EEPROM cell, and to minimize disturbing a programmed logic state of flash EEPROM cells connected to a commonly selected bit-line. A separate zener diode (17) provides a regulated voltage for a selected word-line (40) during programming. By regulating the voltage of the word-line during programming, a program disturb problem associated with a high voltage word-line is minimized.

Abstract: A single transistor EEPROM cell utilizes a tunneling oxide erase mechanism in which the tunneling oxide overlies a portion of the channel region. In addition, an array of single transistor EEPROM cells having a layout which provides convenient byte-at-a-time erase and program operation is disclosed. Two bytes of the array along adjacent rows share a common source, which also forms the source of a pair of erase select transistors, one for each byte. The word lines/control gates of the two bytes form the gates of the two erase select transistors.