Abstract: An automatic gain control (AGC) system (100) for a controlled gain receiver (1101) includes a magnitude generator (160) and a gain corrector (170). The magnitude generator (160) generates a binary voltage squared signal (165) having a binary value that is directly proportional to a recovered signal power of an intercepted signal (113). The gain corrector (170) determines an adjustment of a gain control value (195) as a multiple of increments that are approximately 3 decibel (dB), by shifting (475, 445) a reference threshold by one or more bits and comparing (485, 455) the shifted reference threshold to the binary voltage squared signal. An initial setting of a state of a step attenuator (114) during a track mode (172) is determined during a warm up mode (171) by comparing the binary voltage squared signal (165) to two different thresholds (245, 255). A filter (162) accommodates a variety of bandwidths and symbol rates by settings of an accumulator (505) and scaler (510) that are included in the filter (162).

Abstract: A correlation demodulator unit (20) having gain normalization includes a correlation demodulator (12) for receiving a signal from a receiver (8). The correlation demodulator has a plurality of correlators (C1-CN) corresponding to a plurality of N correlator outputs. A gain normalizer (15) is coupled to the correlation demodulator for accumulating symbol energy on a symbol by symbol basis for each of the plurality of correlator outputs based upon a current symbol decision providing at least an accumulated value within an accumulator (43) for the plurality of correlators and for normalizing the plurality of N correlator outputs using the accumulated value(s).

Abstract: An automatic gain control (AGC) system (100) for a controlled gain receiver (1101) includes a magnitude generator (160) and a gain corrector (170). The magnitude generator (160) generates a binary voltage squared signal (165) having a binary value that is directly proportional to a recovered signal power of an intercepted signal (113). The gain corrector (170) determines an adjustment of a gain control value (195) as a multiple of increments that are approximately 3 decibel (dB), by shifting (475, 445) a reference threshold by one or more bits and comparing (485, 455) the shifted reference threshold to the binary voltage squared signal. An initial setting of a state of a step attenuator (114) during a track mode (172) is determined during a warm up mode (171) by comparing the binary voltage squared signal (165) to two different thresholds (245, 255).

Abstract: A signal processor (125) for recovering data symbols from a received signal includes matched filters (210, 215) for receiving and filtering a quadrature (Q) signal component of the received signal. A detector (225) is coupled to the matched filters (210, 215) for selecting a filtered signal provided by one of the matched filters (210, 215) and for labeling the filtered signal according to a magnitude and phase of the filtered signal to provide a Q channel output flag. A Q channel symbol/sign decoder (235) then processes the Q channel output flag to generate a Q channel magnitude variable and a polarity variable, and a symbol decoder (240) coupled to the Q channel symbol/sign decoder (235) generates a data symbol in accordance with the Q channel magnitude variable and the polarity variable.

Abstract: An automatic simulcast correction method (300) for a selective call receiver (100) includes the steps of measuring a received signal (304) for a received signal strength indication measurement and then determining if a protocol indicates a simulcast signal (310). If the received signal strength indication measurement is above a predefined threshold and the protocol indicates the simulcast signal, then the selective call receiver is optimized for simulcast delay spread distortion (312). If the received signal strength indication measurement is below a predefined threshold or the protocol does not indicate the simulcast signal, then the selective call receiver is optimized for static sensitivity (314).

Abstract: A DC offset correction circuit (68) provides DC offset correction within a receiver (50) for receiving and processing a radio frequency signal (28) within a radio communication system (30). The DC offset correction circuit (68) includes a feedback loop (88) for shifting a digital signal (80) by a programmable amount; and a coarse DC offset correction path (104) coupled to the feedback loop (88) for performing coarse DC offset correction.

Abstract: A full serial implementation of a M-level correlation based demodulator (100) includes a two's complement, pass-through, zero-out complex conjugate multiplier element (102), a boxcar filter (104) coupled to the multiplier element, a complex magnitude approximater element (106) coupled to the boxcar filter and a maximum value and index holding element (108). The multiplier element reuses common products along an M-level of cross-correlation to reduce multiplication functions at a rate 2 times M faster than a sampling rate at an input of the demodulator.

Abstract: A method (200) of decoding a multi-level synchronous protocol having a first portion encoded as M/2-level signals and a subsequent portion encoded as M/2-level signal or M-level signals, wherein the M/2-level signals have expected larger than normal variation of deviations includes steps of decoding (202) the first portion using a biased mode which uses M correlators shifted (204) to adequately cover the frequency range of the expected larger than normal variation of deviations and determining (206) from decoding of the first portion whether the subsequent portion is the M/2-level or M-level signal. If a M/2-level signal is found, continue decoding (210) in the biased mode. If it's the M-level signal, then decoding continues in standard mode (214), which uses M correlators that are spaced in frequency to match M spectral deviations within a predetermined frequency range.

Abstract: A selective call receiver unit (700) capable of reducing data distortion and improving simulcast reception includes a selective call receiver (20), a demodulator (30) coupled to the selective call receiver and a circuit (36 and 300) coupled to the demodulator for reducing data distortion received at a selective call receiver. The circuit includes a detector (350) for detecting a simulcast signal, a filter (351) for windowing the symbol edge area in the simulcast signal providing a windowed symbol edge area, and a clipping circuit (36) for clipping the windowed symbol edge area.

Abstract: A method (900) and circuit (400) for automatic frequency correcting a frequency modulated (FM) digital signal determines a frequency offset value of the detected FM signal during a preamble portion of the FM digital signal, generates an offset corrected signal by removing the frequency offset value from a detected FM signal (440), and generates a frequency corrected signal (460). The frequency corrected signal is generated by selecting the offset corrected signal during the preamble portion, selecting the detected FM signal after the end of the preamble portion when a magnitude of the frequency offset value of the detected FM signal is below a predetermined threshold (445), and otherwise selecting the offset corrected signal after the end of the preamble portion.

Abstract: A circuit (12) for symbol decision directed feedback synchronization includes a current synchonization clock (45) that provides an initial sampling point and selects a detector corresponding to a current symbol decision. The circuit further includes a plurality of detectors (31, 32, 33, and 34) including the detector corresponding to the current symbol decision, a buffer (736) for storing the output of the detector corresponding to the current symbol decision and a processor (300) for seeking within a predetermined window about the initial sampling point for an optimum phase value to provide an adjustment signal which is used by the processor to adjust a subsequent symbol's sychronization clock to provide an optimal sampling point.

Abstract: A method (500) of baud detection in a communication device (700) includes the steps of sorting phase pulses among overlapping sets of time slots (502) and counting phase pulses within each of the overlapping sets of time slots creating corresponding counter values (504). Then, counter values are compared with predetermined thresholds (506-512), wherein a baud pass condition (570) is met when at least one counter has a counter value exceeding an upper threshold and wherein a counter N/2 positions away has a counter value below a lower threshold. The baud pass condition may he further conditioned on meeting the requirement that at least another counter value falls below a middle threshold.

Abstract: A symbol synchronizer (10) for use in a communication device. The symbol synchronizer (10) comprises a sampling circuit (100) which samples the demodulated signal at a plurality of sampling events for each symbol period to generate three sample values at each sampling event. An eye pattern detector circuit (200) generates eye pattern characteristic information based on the three sample values, and outputs a symbol pulse in response to detecting eye pattern characteristic information consistent with a symbol center. A synchronization noise mask circuit (400) filters symbol pulses that occur during a predetermined period of time after a first symbol pulse is detected for each symbol period. A synchronization adjust circuit (500) generates a synchronization pulse during each symbol period at a particular instant of time during the symbol period based on a history of the occurrences of symbol pulses for a current symbol period and for prior symbol periods.

Abstract: A circuit (350) for detecting simulcast channel conditions includes a symbol center averaging circuit (308) for providing a center count of excursions above and below at least a first predetermined threshold and for providing a moving average of the center count over a predetermined number of symbol periods and a symbol edge averaging circuit (310) for providing an edge count of excursions above and below at least a second predetermined threshold and for providing a moving average of the edge count over a predetermined number of symbol periods. Finally, the circuit further includes a comparison circuit (360) programmed to receive and compare the moving average of the center count and the moving average of the edge count to provide a control signal (380) for simulcast detection.

Abstract: A selective call receiver (800), including a receiver circuit (101) and a processor (810), is used for synchronizing an internal reference to symbol edges of a plurality of symbols in a multi-level radio signal transmitted by a radio communication system. To perform this function the processor (810) is adapted to cause the receiver circuit (101) to demodulate the multilevel radio signal to in-phase and quadrature signals (108, 106), convert the in-phase and quadrature signals (108, 106) to a sequence of state transitions representative of the plurality of symbols, detect at least one same state transition from the sequence of state transitions, and synchronize the internal reference to the at least one symbol edge of the plurality of symbols based on the at least one same state transition.

Abstract: A clock recovery circuit for recovering a symbol clock (226) includes a level decoder (210) for determining one of a plurality of received states of a demodulated signal (105) during each symbol period of the symbol clock (226). Each of the plurality of received states corresponds to one of at least two modulation levels. The level decoder (210) generates for each of the plurality of received states a sign signal (212) having transitions at central threshold transition times and a magnitude signal (211). An edge selector (220) determines selected central threshold transition times. A synchronizable clock (225) is synchronized by the selected central threshold transition times, resulting in a significant reduction of symbol clock (226) jitter.

Abstract: A selective call unit (800) comprising a receiver (100) and a processor (810) is used for decoding a 2-level radio signal. The processor (810) is adapted to convert in-phase and quadrature signals generated by the receiver (100) to a sequence of state transitions representative of the plurality of symbols. For each symbol in the plurality of symbols, the processor (810) counts the sequence of state transitions during a symbol period, and compares the recorded count to a predetermined threshold, thereby generating a comparison result. The processor (810) then calculates a bit decision threshold level based on an average of the comparison result for each symbol in the plurality of symbols. For each symbol in a plurality of subsequent symbols, the processor (810) then compares the bit decision threshold level to the sequence of state transitions counted during a symbol period to decode a digital logic level therefrom.

Abstract: A battery-powered selective call transceiver, operating in two-way communication with an RF communication system, can be put in a power saving state. A user control on the transceiver allows a user to select the duration of a power saving interval. The transceiver sends to the communication system a signal requesting that the transceiver enter a power saving state for the selected interval. Upon receipt of an acknowledgment signal from the system, the transceiver enters the power saving state.

Abstract: A communication device (400) with a polarization diversity antenna configuration, having a first antenna (410) with a first plane of polarization and a second antenna (412) with a second plane of polarization. Signal strength of a demodulated signal when the antenna switch (420) is coupled to one of the antennas (410, 412) is measured by a signal strength measuring circuit (440) to generate a short-term average signal power (SA) representing signal strength over a first predetermined number of symbol periods, a medium-term average signal power (MA) representing signal strength over a second predetermined number of symbol periods, and a long-term average signal power (LA) representing signal strength over a third predetermined number of symbol periods, greater than the second predetermined number of symbol periods and first predetermined number of symbol periods. Switching between antennas (410, 412) is made in response to differences between SA, MA and LA.

Abstract: A data receiver (110) for processing multiple signals includes a receiving circuit (120) for demodulating at least first and second signals and a selector (125) coupled to the receiving circuit (120) for comparing the at least first and second signals to estimated peak and valley values. The selector (125) generates error values associated with the at least first and second signals and selects a data symbol associated with one of the estimated peak and valley values based on the error values. A timing circuit (140, 150) activates the selector (125) at predetermined times, and a controller (140) coupled to the selector (125) and the timing circuit (140, 150) recovers information in accordance with the data symbol and other data symbols.