Abstract: In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser.

Abstract: In one embodiment, the invention is an integrated circuit (IC) including an OTP memory and conditioning circuitry. The IC receives an externally-generated DC programming voltage signal that the conditioning circuitry transforms into a programming pulse signal for programming the OTP memory. The conditioning circuitry includes: (i) reset protection circuitry for holding the programming pulse signal low if the IC is powering up, (ii) an overvoltage protection circuit for substantially preventing the programming pulse voltage from exceeding predefined boundaries, and (iii) a conversion switch for controlling the programming pulse voltage. The programming pulse voltage is (i) substantially equivalent to the externally-generated DC voltage if an enable signal is on, and (ii) substantially equivalent to a reference voltage if the enable signal is off.

Abstract: An OTP and Reset Assert Counter and a method for protecting one-time programmable memory settings during read-out from an OTP memory block. The OTP memory block is set at ground and in a reset mode with a clock driven External Reset (RSTB) signal set at ground true active. A Delay Counter is programmed with a time delay to correspond with the time that is inherently needed by the OTP Memory block to complete a read-out process that begins with the External Reset (RSTB) signal being set to HIGH; and an input Clock signal is delayed by the Delay Counter for a duration of the time delay that begins with the External Reset (RSTB) signal being set to HIGH.

Abstract: In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser.

Abstract: In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser.

Abstract: A dynamic random access memory has a row conductor boosted in excess of the power supply level during an initial portion of a memory cycle. The voltage is then clamped at the supply level during the middle portion of the cycle, and optionally boosted again during the refresh portion. This allows improved performance and reliability, especially in memories employing bit lines precharged to one-half the power supply level.