Abstract: In an integrated circuit, a system and method of programmably controlling the delay between a second clock signal with respect to a first clock signal after fabricating the integrated circuit. Prior to fabrication, a programmable delay group is formed and will be included in the integrated circuit. The programmable delay group includes a plurality of parallel coupled sets of delay stages. Each set having at least one delay stage. For the sets having more than one delay stage, the delay stages are serially coupled. After fabrication of the integrated circuit and in operation, the first clock signal is applied to one end of each of the sets of delay stages. The enable signals are generated and applied to the programmable delay group in order to enable one of the sets of delay stages. The enabled set delays the first clock signal, thereby producing the second clock signal at the other end of the enabled set and hereby controlling the delay of the second clock signal.

Abstract: Power usage of an integrated circuit including an embedded memory array is reduced significantly by preventing a clock signal from clocking unaccessed memory blocks in the embedded memory array while allowing the clock signal to clock the currently accessed memory block. In an exemplary embodiment, the clock signal is gated with individual memory block enable signals such that the clock signal clocks only the currently enabled or accessed memory block. Only one memory block or a limited number of memory blocks out of an array of memory blocks on a data bus is clocked or operated at any one time. In another embodiment, a delay circuit delays the removal of the clock signal to the accessed memory block until a period of time after the enable signal to the memory block is removed. Thus, the accessed or enabled memory block is allowed to clock internally substantially only during a time corresponding to when that memory block is enabled or accessed.

Abstract: Power usage of an integrated circuit including an embedded memory array is reduced significantly by preventing a clock signal from clocking unaccessed memory blocks in the embedded memory array while allowing the clock signal to clock the currently accessed memory block. In an exemplary embodiment, the clock signal is gated with individual memory block enable signals such that the clock signal clocks only the currently enabled or accessed memory block. Only one memory block or a limited number of memory blocks out of an array of memory blocks on a data bus is clocked or operated at any one time. In another embodiment, a delay circuit delays the removal of the clock signal to the accessed memory block until a period of time after the enable signal to the memory block is removed. Thus, the accessed or enabled memory block is allowed to clock internally substantially only during a time corresponding to when that memory block is enabled or accessed.

Abstract: A multifunctional chip includes first and second electrically isolated bonding pads. The chip also includes a control circuit coupled to the second bonding pad. The control circuit commands the chip to perform the first function if the first and second bonding pads are coupled. Alternatively, the control circuit commands the chip to perform the second function if the first and second bonding pads remain electrically isolated. The coupling or isolation between the first and second bonding pads is determined by wire bonds. Therefore, the use of wire bonds selects the function for the chip.