Abstract: An asymmetric static random access memory cell (50 and 53) includes polysilicon load elements (55 and 56), N-channel pull-down transistors (57 and 58), and N-channel coupling transistors (59 and 60). One of the coupling transistors (59 and 81) has a channel width that is less than the channel width of the other coupling transistor (60 and 80). The asymmetric cells (50 and 53) are located close to power supply voltage terminal V.sub.SS, while conventional symmetrical cells (51 and 52) are located apart from the power supply voltage terminal V.sub.SS. The asymmetric cells (50 and 53) correct an imbalance in the ground path caused by a parasitic resistance (83 and 86) of a diffusion layer (94) that is used to couple the asymmetric cells (50 and 53) to ground potential. The asymmetric cell (50 and 53) improves cell stability without degrading performance or increasing cell area.