Abstract: A circuit for providing a fractional divider/multiplier using harmonic recombination may include a power amplifier, an oscillator coupled to the power amplifier, and a divider coupled to the oscillator. In one or more implementations, the divider is configured to generate one or more phases of a harmonic from the oscillator to reduce signal interference from the power amplifier. In one or more implementations, the divider includes a divide-by-M divider, where M is a positive integer, and an array of transconductance cells coupled to the output of the divide-by-M divider. In one or more implementations, the divider includes an inductor or a filter coupled to the output of the array of transconductance cells. In one or more implementations, the oscillator includes a logical gate and a resistor-capacitor circuit coupled in series feedback with a multi-stage ring oscillator. The oscillator may include a divider coupled to the multi-stage ring oscillator.